No state transition in verilog code

module spi_master #
(
    parameter CLK_DIV_FACTOR = 5'd4
)
(
    input adc_clk,
    input clk_in,
    input rst_in,
   
    input spi_start_signal_in,        //control signal for start
    input [23:0] spi_wr_data_in,      //write data to IC
   
    input spi_wr_en,
    input spi_rd_en,
   
    input spi_miso_in,                //read from IC
    input [1:0] no_of_bits,
   
    output reg [23:0] spi_rd_data_out,  //read data from IC
    output spi_rd_end_out, 
    output spi_wr_end_out,
    output spi_mosi_out,            //write to IC
    output spi_sclk_out                 //spi_Sclk   
   
    );
   
    reg [23:0] wr_data_buff_reg;
    reg [23:0] rd_data_buff_reg;
    reg [4:0] clk_cnt_reg;
    reg r_spi_mosi_out;
    wire clk_valid_reg;
    reg r_spi_clk;
    integer r_spi_clk_div_cntr = 0;
    integer r_no_of_wr_bits_cntr = 0;
    integer r_no_of_rd_bits_cntr = 0;
    reg r_spi_wr_end_out;
    reg r_spi_rd_end_out;
    integer r_no_of_bits = 0;
   
    parameter     ST_IDLE      = 3'b000,
                ST_SCLK_HIGH = 3'b001,
                ST_SCLK_LOW  = 3'b010,
                ST_DATA_TX   = 3'b011;
    reg [1:0] spi_wr_state, spi_wr_nxt_state, spi_rd_state;
   
//    assign r_no_of_bits = {(no_of_bits == 2'b00) ? 24 : (no_of_bits == 2'b01) ? 16 : 8};
    assign spi_wr_end_out     = r_spi_wr_end_out;
    assign spi_Sclk            = r_spi_clk;
    assign spi_mosi_out        = r_spi_mosi_out;
    assign spi_rd_end_out     = r_spi_rd_end_out;
   
    always @(posedge clk_in or posedge rst_in)
    begin
        if(rst_in == 1'b1) begin
            r_no_of_bits <= 0;
            spi_wr_state <= ST_IDLE; end
        else begin
            spi_wr_state <= spi_wr_nxt_state;
            r_no_of_bits <= {(no_of_bits == 2'b00) ? 24 : (no_of_bits == 2'b01) ? 16 : 8}; end
    end 
           
    always @(posedge clk_in or posedge rst_in)
    begin
        if(rst_in == 1'b1) begin
            r_spi_mosi_out          <= 1'b0;
            spi_wr_nxt_state        <= ST_IDLE;
            r_spi_clk                <= 1'b0;
            wr_data_buff_reg[23:0]     <= 24'd0;
            r_spi_wr_end_out        <= 1'b0;
            r_no_of_wr_bits_cntr    <= 0;
            r_spi_clk_div_cntr        <= 0; end
        else begin
//            if(spi_wr_en == 1'b1) begin
            case (spi_wr_state)
            ST_IDLE:    begin
                            r_spi_wr_end_out        <= 1'b0;
                            r_no_of_wr_bits_cntr    <= 0;
                            r_spi_mosi_out          <= 1'b0;
                            if(spi_wr_en == 1'b1)
                              spi_wr_nxt_state        <= ST_DATA_TX;
                            else
                              spi_wr_nxt_state        <= ST_IDLE;
//                            r_spi_clk                <= 1'b0;
                            wr_data_buff_reg[23:0]     <= spi_wr_data_in[23:0]; end
            ST_DATA_TX:    begin
                        if(r_no_of_wr_bits_cntr < r_no_of_bits) begin
                            r_spi_mosi_out          <= wr_data_buff_reg[23];
                            spi_wr_nxt_state        <= ST_SCLK_HIGH;
                            wr_data_buff_reg[23:0]     <= {wr_data_buff_reg[22:1], 1'b0}; end
                        else begin
                            r_spi_wr_end_out        <= 1'b1;
                            r_spi_mosi_out          <= 1'b0;
                            spi_wr_nxt_state        <= ST_IDLE;
                            wr_data_buff_reg[23:0]     <= 24'b0; end end   
            ST_SCLK_HIGH:begin
                            r_spi_clk                <= 1'b1;
                            r_no_of_wr_bits_cntr    <= r_no_of_wr_bits_cntr + 1;
                            if(r_spi_clk_div_cntr == (CLK_DIV_FACTOR >> 1) - 1)
                            begin
                                r_spi_clk_div_cntr    <= 0;
                                spi_wr_nxt_state    <= ST_SCLK_LOW; end
                            else begin
                                r_spi_clk_div_cntr    <= r_spi_clk_div_cntr + 1;
                                spi_wr_nxt_state    <= ST_SCLK_HIGH; end end   
            ST_SCLK_LOW:begin
                            r_spi_clk                <= 1'b0;
                            if(r_spi_clk_div_cntr == (CLK_DIV_FACTOR >> 1) - 2)
                            begin
                                r_spi_clk_div_cntr    <= 0;
                                spi_wr_nxt_state    <= ST_DATA_TX; end
                            else begin
                                r_spi_clk_div_cntr    <= r_spi_clk_div_cntr + 1;
                                spi_wr_nxt_state    <= ST_SCLK_LOW; end end
            default  : spi_wr_nxt_state    <= ST_IDLE;                   
            endcase end
//        end
    end