No matching overload in VHDL

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Im getting :32:14:32:24|No matching overload for "<" error for the following code
Code VHDL - [expand]
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Process (clk, RST)  
BEGIN
     IF RST = '0' THEN
        
        acc <= (Others => '0') ;
     ELSIF (Clk = '1' and Clk'event)  THEN
        If acc = max THEN  
           
           acc <= (others => '0') ;
        ELSE
          acc <= acc + '1' ;
          output <= acc < input;
        END IF ;
     END IF ; 
END PROCESS ;


Im using std_logic_signed .
 
Last edited by a moderator:

Re: No matching overload error

acc < input
returns a boolean, not a std_logic. Unless output is declared as a boolean, you have to write it like this:

Code: 
if acc < input then
  output <= '1';
else
  output <= '0';
end if;

or if you have a VHDL 2008 compliant compiler (very unlikely) you can write:

output <= '1' when (acc < input) else '0';
 

That line: "output<=acc<input" doesn't look right. What is the type of output, input? Are you trying to set output to 1 if acc is less than input? If so, try using an if statement.

Code: 
        If acc< input then
           output<='1';
        else
          output<='0';
        end if;
 

Re: No matching overload error

thank you. Can you tell me exactly what are the merits of VHDL over verilog (not text book answers) application wise
 

Re: No matching overload error

They are both different. Some love VHDL, some love verilog. But they both do the same things. You need to chose which one you prefer.
 

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