nMOS passing 1's poorly

Vaibhav Sundriyal · Feb 1, 2014

Hi,

I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly".
What exactly do these statements mean and why is it so? Also, what is the reason that AND and OR gate can't be simply formed but they have
to be formed as AND=NAND->NOT and OR=NOR->NOT?

Thanks

lostinxlation · Feb 1, 2014

A channel of a nMOS turns off when gate-source or gate-drain voltage becomes smaller than threshold voltage. Keep this in mind...
Imagine that you have a nMOS pass transistor where gate=0, source=1 and drain=0. Now you apply 1 on the gate which leads the nMOS to turn on and the current starts flowing from source to drain. If there is no path to the ground at drain side, the voltage level at drain goes up and eventually gate-drain voltage comes down to the threshold voltage, which turns off the nMOS. In this scenario, the drain NEVER reach true 1(VDD), instead, it only reaches (VDD - threshold voltage). This doesn't happen when you pass 0 through nMOS, since either of gate-source or gate-drain voltage is always higher than threshold voltage and the nMOS stays on as long as 1 is applied on gate.

I don't know if you should call it poor to pass 1 through nMOS, but that's what your book is trying to say.

Vaibhav Sundriyal · Feb 1, 2014

lostinxlation said:
A channel of a nMOS turns off when gate-source or gate-drain voltage becomes smaller than threshold voltage. Keep this in mind...
Imagine that you have a nMOS pass transistor where gate=0, source=1 and drain=0. Now you apply 1 on the gate which leads the nMOS to turn on and the current starts flowing from source to drain. If there is no path to the ground at drain side, the voltage level at drain goes up and eventually gate-drain voltage comes down to the threshold voltage, which turns off the nMOS. In this scenario, the drain NEVER reach true 1(VDD), instead, it only reaches (VDD - threshold voltage). This doesn't happen when you pass 0 through nMOS, since either of gate-source or gate-drain voltage is always higher than threshold voltage and the nMOS stays on as long as 1 is applied on gate.

I don't know if you should call it poor to pass 1 through nMOS, but that's what your book is trying to say.

Thanks much for your reply.

Imagine that you have a nMOS pass transistor where gate=0, source=1 and drain=0. Now you apply 1 on the gate which leads the nMOS to turn on and the current starts flowing from source to drain. If there is no path to the ground at drain side

Doesn't drain=0 means that drain is connected to GND?

Am I correct in assuming that by passing 0 or 1 means applying input 0 or 1 at the gate terminal?

Thanks

lostinxlation · Feb 1, 2014

Vaibhav Sundriyal said:
Doesn't drain=0 means that drain is connected to GND?

If 0 state is carried over from the previous cycle, the drain remains 0 without directly being grounded at that moment.

Am I correct in assuming that by passing 0 or 1 means applying input 0 or 1 at the gate terminal?

Thanks

I meant applying 0 or 1 on the source terminal.

nMOS passing 1's poorly

Vaibhav Sundriyal

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lostinxlation

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Vaibhav Sundriyal

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lostinxlation

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