nMOS diode for ESD? the area of these transistors?

Hi,

I want to make a simple ESD circuit using two diodes clamped to VDD and GND. I am using nMOS transistor to configure these diodes. But, I don't know how big these transistor should be? I have seen in some ESD something like L=10um and W=10um but don't know what are the variables that are considered to get these values.

Also, if I am using wide transistor ( L=10um), is there anyway to composite it from smaller transistors just like high Width (W=10um) where we can use multiple 1um transistors and connect them in parallel to get one transistor with big W. From structure point of view, it seems we can't do that, what do you think?

MOSFETs as diodes are generally inferior, as far as dI/dV
(1/Rs) per area goes, to PN diodes. The main reason to
use a FET is that nobody cared enough to support diodes
in the PDK. But a well run foundry would have all necessary
ESD elements in the main device library, I/O library or ESD
library of the kit.

What you want, is to close the ESD current loop at as
low an on-chip voltage drop as possible (and certainly lower
than BVox(short pulse)). So figure your threat current first.
For classic HBM ESD that's Vthreat/1500ohms. Trickier for
MM, CDM. Then find the tolerable gate ox stress (and do
not neglect punchthrough of min-L devices, which could
pick up either thermal damage or hot carrier drift by non-
oxide-conduction). Allocate that voltage to "up diode,
clamp, up diode" around the loop.

Now work the device l, w, nf, m to get the right Vf(peak)
(bearing in mind that devices that will break down, like a
GGNMOS core clamp, need silicide block to ballast any hot
spotting, which adds ohmic resistance but is almost never
modeled in this aspect, for a core library device - this is
an ESD-specific device modification). You can calculate it
based on L/W*rho({N+, P+} once you get close and if you
co-parameterize it with the FET(s) then it can just "fall out
of" optimization loop.

You never ever want to use a super-wide single stripe
because the longitudinal resistance down the S, D metal
adds to series-R while applying high pulsed current density.
Your failure mode then becomes interconnect fusing or a
crater near the first contact inside the active area,
rather than oxide rupture. Multiple fingers and heavy
strapping is wanted. The silicide pullback can give you
room to add metal width, but parallel is where it's at.

GGNMOS clamp L should be shorter or equal to the
shortest devices used in the chip. No reason for a
MOS diode to be longer than minimum either, if the
circuitry uses min L at max rated supply / signal
voltage.