Nexys2 board 7 segment display

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xilinx1001

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Hi,

I am working on 7 segment display of nexys2 board

Code:
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(7 downto 0)
        --dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0);
	 signal i: STD_LOGIC;
	 

	 --signal sw: STD_LOGIC_VECTOR(3 downto 0);
	 --signal sw1: STD_LOGIC_VECTOR(7 downto 4);

begin

    anodes <= r_anodes;
	 
    -- Given Binary Value print it
     process(counter,switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" => r_anodes <= "1110"; -- AN 0
            when "01" => r_anodes <= "1101"; -- AN 1
            when "10" => r_anodes <= "1011"; -- AN 2
            when "11" => r_anodes <= "0111"; -- AN 3

            when others => r_anodes <= "1111"; -- nothing
				end case;

--        -- Set segments correctly
          case r_anodes is
          when "1110" => 

                  if switches(7 downto 4) = "0000"  then
                  sevenseg <= "1000000"; -- 0
                  elsif switches(7 downto 4) = "0001" then
                  sevenseg <= "1111001"; -- 1
				      elsif switches(7 downto 4) = "0010" then
                  sevenseg <= "0100100"; -- 2
				      elsif switches(7 downto 4) = "0011" then
                  sevenseg <= "0110000"; -- 3
				      elsif switches(7 downto 4) = "0100" then
                  sevenseg <= "0011001"; -- 4
					   elsif switches(7 downto 4) = "0101" then
                  sevenseg <= "0010010"; -- 5
						elsif switches(7 downto 4) = "0110" then
                  sevenseg <= "0000010"; -- 6
						elsif switches(7 downto 4) = "0111" then
                  sevenseg <= "1111000"; -- 7
						elsif switches(7 downto 4) = "1000" then
                  sevenseg <= "0000000"; -- 8
						elsif switches(7 downto 4) = "1001" then
                  sevenseg <= "0010000"; -- 9
						elsif switches(7 downto 4) = "1010" then
                  sevenseg <= "0001000"; -- A
						elsif switches(7 downto 4) = "1011" then
                  sevenseg <= "0000011"; -- B
						elsif switches(7 downto 4) = "1100" then
                  sevenseg <= "1000110"; -- C
						elsif switches(7 downto 4) = "1101" then
                  sevenseg <= "0100001"; -- D
						elsif switches(7 downto 4) = "1110" then
                  sevenseg <= "0000110"; -- E
						else
						sevenseg <= "0001110";
						end if;
						r_anodes<="1110";
						
				
            when "1101" => 
				      if switches(3 downto 0) = "0000"  then
                  sevenseg <= "1000000"; -- 0
                  elsif switches(3 downto 0)  = "0001" then
                  sevenseg <= "1111001"; -- 1
				      elsif switches(3 downto 0)  = "0010" then
                  sevenseg <= "0100100"; -- 2
				      elsif switches(3 downto 0)  = "0011" then
                  sevenseg <= "0110000"; -- 3
				      elsif switches(3 downto 0)  = "0100" then
                  sevenseg <= "0011001"; -- 4
					   elsif switches(3 downto 0)  = "0101" then
                  sevenseg <= "0010010"; --5
						elsif switches(3 downto 0)  = "0110" then
                  sevenseg <= "0000010"; -- 6
						elsif switches(3 downto 0)  = "0111" then
                  sevenseg <= "1111000"; -- 7
						elsif switches(3 downto 0)  = "1000" then
                  sevenseg <= "0000000"; -- 8
						elsif switches(3 downto 0)  = "1001" then
                  sevenseg <= "0010000"; -- 9
						elsif switches(3 downto 0)  = "1010" then
                  sevenseg <= "0001000"; -- A
						elsif switches(3 downto 0)  = "1011" then
                  sevenseg <= "0000011"; -- B
						elsif switches(3 downto 0)  = "1100" then
                  sevenseg <= "1000110"; -- C
						elsif switches(3 downto 0)  = "1101" then
                  sevenseg <= "0100001"; -- D
						elsif switches(3 downto 0)  = "1110" then
                  sevenseg <= "0000110"; -- E
						else
						sevenseg <= "1111111";
						
						
						 end if;
						 r_anodes<="1101";

						when others => sevenseg <= "1111111"; -- nothing

					end case;
					end process;


   
--
    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            -- Iterate
            counter <= counter + 1;
        end if;
    end process;

end Behavioral;

This code is working

But the problem is that, it is showing only the case "1101" (2nd case) on 7 segment

May be I need to use delay after "1110"

I tried with wait,but do not work.

Error:
ERROR:HDLParsers:808 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 80. / can not have such operands in this context.
ERROR:HDLParsers:1015 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 80. Wait for statement unsupported.
ERROR:HDLParsers:1405 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 80. statement WAIT not allowed in a process with a sensitivity list

Any suggestion is appreciated
 

yes, you cant have wait - its quite self explanitory.
So, this has become a debugging problem. Have you written a testbench and simulated your design?
 

TrickyDicky said:
yes, you cant have wait - its quite self explanitory.
So, this has become a debugging problem. Have you written a testbench and simulated your design?
Click to expand...

what I can use instead of wait in VHDL

can I use for loop for delay in vhdl

I have not tried with testbench

- - - Updated - - -

Hi,

Thanks for ur reply

I tried with test bench

I am getting some thing like in the picture

both the anodes are working(which means both 7 segment displays are ON)

but I could not see the 1st one in practical
 
Last edited:

you cannot do a delay with wait or a loop. You'll need a counter running and wait until it reaches a certain value if you need to delay.
 

xilinx1001 said:
can I use for loop for delay in vhdl
Click to expand...

No. Read the docs on what LOOP does. As TrickyDicky said, you'll need a counter.

I tried with test bench

I am getting some thing like in the picture
Click to expand...

Best post the actual testbench code.

Because now we can only guess why you get XX's there. Random guess: because you forgot initial conditions for some registers.
 

Yes, my clock frequency is 50 M hz

It is very fast. so thats why I cannot see the result here

So, how can I delay the counter for some time

Again I cannot use wait statement here
 
Last edited:

How can you delay the counter for some time? Indeed by using clock enables. But my mother taught me to never believe someone actually intended the question as asked. Because if you start the thread with "oh noez, how do I introduce a delay" and then suddenly that becomes "oh noez, how do I delay my counter" then you didn't understand the purpose of the suggested counter.

You want to have REAL HARDWARE (as opposed to simulation fluff) that waits for a certain amount of time. For that you need a counter. Counter counts at 50 MHz in your case. Which means 20 ns clock periods. So suppose you want to wait for 100 ns then you need a counter that can count to 5, and then generates a pulse that tells you "hey, the 100 ns wait is over. go do something".
 

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