Nexys2 board 7 segment display

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xilinx1001

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Hi,

I am working on nexys2 board 7 segment display

I need to display the binary value of first 4 switches on one 7 segment display

And binary value of next 4 switches on another 7 segment display

I wrote a code for this

But I have some errors in the implementation

Any help is appreciated

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(6 downto 0)
        --dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0);
begin

    anodes <= r_anodes;

    -- Given Binary Value print it
    multiplex: process(counter,switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" => r_anodes <= "1110"; -- AN 0
            when "01" => r_anodes <= "1101"; -- AN 1
            when "10" => r_anodes <= "1011"; -- AN 2
            when "11" => r_anodes <= "0111"; -- AN 3

            when others => r_anodes <= "1111"; -- nothing
				end case;

--        -- Set segments correctly
        case r_anodes is
          when "1110" => 


               if switches(3 downto 0) = x"0"  then
                   sevenseg <= "1111001"; -- 1
               else switches(3 downto 0) = x"1"  then
                  sevenseg <= "1000000"; -- 0
               end if;
            when "1101" => 
                if switches(3 downto 0) = '1' then
                    sevenseg <= "1111001"; -- 1
                else
                    sevenseg <= "1000000"; -- 0
                end if;
            when "1011" => 
                if switches(3 downto 0) = '1' then
                    sevenseg <= "1111001"; -- 1
                else
                    sevenseg <= "1000000"; -- 0
                end if;
            when "0111" => 
                if switches(3 downto 0) = '1' then
                    sevenseg <= "1111001"; -- 1
                else
                    sevenseg <= "1000000"; -- 0
                end if;
when others => sevenseg <= "1111111"; -- nothing
        
					end case;
					end process;

   

    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            -- Iterate
            counter <= counter + 1;
        end if;
    end process;


end Behavioral;


Errors:

ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 44. parse error, unexpected THEN, expecting SEMICOLON
ERROR:HDLParsers:808 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 48. = can not have such operands in this context.
ERROR:HDLParsers:808 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 54. = can not have such operands in this context.
ERROR:HDLParsers:808 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 60. = can not have such operands in this context.
 

heres the problem:

if switches(3 downto 0) = '1' then

'1' is a single bit. You cannot compare 4 bits to a single bit. You need to make the compare value an array:

if switches(3 downto 0) = "0001" then

etc.
 

TrickyDicky said:
heres the problem:

if switches(3 downto 0) = '1' then

'1' is a single bit. You cannot compare 4 bits to a single bit. You need to make the compare value an array:

if switches(3 downto 0) = "0001" then

etc.
Click to expand...

Hi,

I tried it and removes some errors

But still I have a error

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(6 downto 0)
        --dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0)
	);

begin

    anodes <= r_anodes;
	 --switches(3 downto 0) <= sw;
	 

    -- Given Binary Value print it
    multiplex: process(counter,switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" => r_anodes <= "1110"; -- AN 0
            when "01" => r_anodes <= "1101"; -- AN 1
            when "10" => r_anodes <= "1011"; -- AN 2
            when "11" => r_anodes <= "0111"; -- AN 3

            when others => r_anodes <= "1111"; -- nothing
				end case;

--        -- Set segments correctly
        case r_anodes is
          when "1110" => 


               if switches(3 downto 0) = "0001"  then
                   sevenseg <= "1111001"; -- 1
               else 
                  sevenseg <= "1000000"; -- 0
               end if;
            
					end case;
					end process;

   

    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            -- Iterate
            counter <= counter + 1;
        end if;
    end process;


end Behavioral;

ERROR:HDLParsers:812 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 41. A value is missing in case.
 

with a case statement, you must cover ALL cases. Your case statement for r_anodes only cover 1 case. The previous code covered all cases.
 

TrickyDicky said:
with a case statement, you must cover ALL cases. Your case statement for r_anodes only cover 1 case. The previous code covered all cases.
Click to expand...
Hi,

Now I replaced with all the cases that are possible

Again I am getting errors like this:

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(6 downto 0)
        --dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0);
	 --signal sw: STD_LOGIC_VECTOR(3 downto 0);

begin

    anodes <= r_anodes;
	 --switches(3 downto 0) <= sw;
	 

    -- Given Binary Value print it
    multiplex: process(counter,switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" => r_anodes <= "1110"; -- AN 0
            when "01" => r_anodes <= "1101"; -- AN 1
            when "10" => r_anodes <= "1011"; -- AN 2
            when "11" => r_anodes <= "0111"; -- AN 3

            when others => r_anodes <= "1111"; -- nothing
				end case;

--        -- Set segments correctly
        case r_anodes is
          when "1110" => 


               if switches(3 downto 0) = "0000"  then
                   sevenseg <= "1111001"; -- 1
               else switches(3 downto 0) = "0001"  
                  sevenseg <= "1000000"; -- 0
						
               end if;
            when "1101" => 
                if switches(3 downto 0) = "0001" then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0010" 
                    sevenseg <= "1000000"; -- 0
                end if;
            when "1011" => 
                if switches(3 downto 0) = '0001' then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0001" 
                    sevenseg <= "1000000"; -- 0
                end if;
            when "0111" => 
                if switches(3 downto 0) = '0001' then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0001" 
                    sevenseg <= "1000000"; -- 0
                end if;
when others => sevenseg <= "1111111"; -- nothing
        
					end case;
					end process;


   

    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            -- Iterate
            counter <= counter + 1;
        end if;
    end process;


end Behavioral;

Errors:
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 47. parse error, unexpected IDENTIFIER, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 50. parse error, unexpected TICK
 

single quotes ' mean single character. You need double quotes "" to represent a string.
 

Hi,

Thanks for ur reply

I fixed it but again saying that I have some errors


Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
    port(
        clock       : in STD_LOGIC;
        sevenseg    : out STD_LOGIC_VECTOR(6 downto 0);
        anodes  : out STD_LOGIC_VECTOR(3 downto 0);
        switches    : in STD_LOGIC_VECTOR(6 downto 0)
        --dp      : in STD_LOGIC
    );
end main;

architecture Behavioral of main is
    signal counter: STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
    signal r_anodes: STD_LOGIC_VECTOR(3 downto 0);
	 --signal sw: STD_LOGIC_VECTOR(3 downto 0);

begin

    anodes <= r_anodes;
	 --switches(3 downto 0) <= sw;
	 

    -- Given Binary Value print it
    multiplex: process(counter,switches)
    begin
        -- Set anode correctly
        case counter(1 downto 0) is
            when "00" => r_anodes <= "1110"; -- AN 0
            when "01" => r_anodes <= "1101"; -- AN 1
            when "10" => r_anodes <= "1011"; -- AN 2
            when "11" => r_anodes <= "0111"; -- AN 3

            when others => r_anodes <= "1111"; -- nothing
				end case;

--        -- Set segments correctly
        case r_anodes is
          when "1110" => 


               if switches(3 downto 0) = "0000"  then
                   sevenseg <= "1111001"; -- 1
               else switches(3 downto 0) = "0001"  
                  sevenseg <= "1000000"; -- 0
						
               end if;
            when "1101" => 
                if switches(3 downto 0) = "0001" then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0010" 
                    sevenseg <= "1000000"; -- 0
                end if;
            when "1011" => 
                if switches(3 downto 0) = "0001" then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0001" 
                    sevenseg <= "1000000"; -- 0
                end if;
            when "0111" => 
                if switches(3 downto 0) = "0001" then
                    sevenseg <= "1111001"; -- 1
                else switches(3 downto 0) = "0001" 
                    sevenseg <= "1000000"; -- 0
                end if;
when others => sevenseg <= "1111111"; -- nothing
        
					end case;
					end process;


   

    countClock: process(clock, counter)
    begin
        if rising_edge(clock) then
            -- Iterate
            counter <= counter + 1;
        end if;
    end process;


end Behavioral;

Errors:
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 47. parse error, unexpected IDENTIFIER, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 54. parse error, unexpected IDENTIFIER, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 60. parse error, unexpected IDENTIFIER, expecting SEMICOLON
ERROR:HDLParsers:164 - "C:/Users/Vivek Alaparthi/Desktop/Xilinx projects/display2/display.vhd" Line 66. parse error, unexpected IDENTIFIER, expecting SEMICOLON
 

you forgot some "then"

from now on - please read the errors yourself. They are usually pretty helpful.
 

TrickyDicky said:
you forgot some "then"

from now on - please read the errors yourself. They are usually pretty helpful.
Click to expand...


Hi,

There is no need of then for else

If it is elsif then there is a need of then

I dont know why this code is showing error
 

But you also cannot have a condition on the else. you must use elseif or remove the condition:

Code: 
if switches(3 downto 0) = "0001" then
  sevenseg <= "1111001"; -- 1
else
  sevenseg <= "1000000"; -- 0
end if;
 

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