joe2moon
Full Member level 5
CUPERTINO, Calif.?(BUSINESS WIRE)?April 26, 2004? Giga Scale Integration Corporation (Giga Scale IC(TM)) today took the wraps off the InCyte(R) product family, its next-generation Integrated Circuit (IC) specification system that allows users to optimize between conflicting design goals -- die size, power, leakage, speed, yield and cost.
During chip creation, design teams want to optimize key elements, including logic and analog intellectual property (IP), embedded memory and repair, I/Os, power leakage and switching activity. Managers and architects need a quick, accurate method to compare and visualize various tradeoffs in library characteristics, semiconductor process nodes, memory configurations and IP.
InCyte includes a specification cockpit, estimation engine, floorplan generator, performance calculator and compare display, driven by a Giga Scale IC-proprietary Technology Macro Modeler (TMM). Bundled with a portfolio of libraries -- from 90nm to 0.35um -- and a broad family of hard and soft IP macros, users have a system with insight into available offerings from semiconductor vendors.
InCyte creates a Silicon Virtual Model(TM) (SVM) in industry standard process nodes or specific foundry/library vendor combination. It uses a graphical user interface (GUI) to replace spreadsheets for IC estimation. Users identify their target process nodes and libraries; define clock domains and voltage zones; select I/O pads and bonding styles; describe logic blocks; and select hard and soft IP. Since it's web-enabled, they can select from available libraries, memory compilers and hundreds of IP options optimized for their particular need and have updated information for the latest processes.
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The InCyte product family will be demonstrated at the 41st Design Automation Conference (DAC) in Booth Number 4339 from Monday, June 7, through Wednesday, June 9, at the San Diego Convention Center in San Diego, Calif.
Pricing and Availability
The InCyte product family is available now, and runs on Windows, Sun, Linux, or Mac OS X machine.
For more information, please see www.gigaic.com.
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https://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=122809
During chip creation, design teams want to optimize key elements, including logic and analog intellectual property (IP), embedded memory and repair, I/Os, power leakage and switching activity. Managers and architects need a quick, accurate method to compare and visualize various tradeoffs in library characteristics, semiconductor process nodes, memory configurations and IP.
InCyte includes a specification cockpit, estimation engine, floorplan generator, performance calculator and compare display, driven by a Giga Scale IC-proprietary Technology Macro Modeler (TMM). Bundled with a portfolio of libraries -- from 90nm to 0.35um -- and a broad family of hard and soft IP macros, users have a system with insight into available offerings from semiconductor vendors.
InCyte creates a Silicon Virtual Model(TM) (SVM) in industry standard process nodes or specific foundry/library vendor combination. It uses a graphical user interface (GUI) to replace spreadsheets for IC estimation. Users identify their target process nodes and libraries; define clock domains and voltage zones; select I/O pads and bonding styles; describe logic blocks; and select hard and soft IP. Since it's web-enabled, they can select from available libraries, memory compilers and hundreds of IP options optimized for their particular need and have updated information for the latest processes.
:
:
:
The InCyte product family will be demonstrated at the 41st Design Automation Conference (DAC) in Booth Number 4339 from Monday, June 7, through Wednesday, June 9, at the San Diego Convention Center in San Diego, Calif.
Pricing and Availability
The InCyte product family is available now, and runs on Windows, Sun, Linux, or Mac OS X machine.
For more information, please see www.gigaic.com.
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https://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=122809