Newbie question for Test-bench.

micktosin · Mar 6, 2014

Hello there, I programmed a code to divide my FPGA clock to my required frequency and then invert into two square wave, however I keep getting an error with the testbench stating "the module pulsegentb(file name) is instantiating itself".
And also with the file reports stating "the instantiation depth of pulsegatetb/notgate/notgate....is 51. This might indicate a recursive instantiation, increasing limit to 75".
Below is the code of the square wave generator and the test bench please can someone help me as to why I can't run the testbench?

Test Bench
///////////////////////////////////////////////////////////////////////////////////////////////////

Code Verilog - [expand]
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module pulsegentb();
wire igbtclk1, igbtclk2;
reg clock, reset;
 
always begin
      #1 clock =!clock;
end
 
initial begin
clock = 0;
reset = 0;
 
#10
$finish; 
end
 
pulsegentb notgate(clock, igbtclock1, igbtclock2);
 
endmodule

Square wave generator
///////////////////////////////////////////////////////////////////////////////////////////////////

Code Verilog - [expand]
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module igbt_clock_gen (clock,reset,igbtclock1,igbtclock2);
input clock,reset;
output reg igbtclock1, igbtclock2;
wire temp1;
 
freq_div f1 (clock,reset,temp1);
clock_multiplier c1 (temp1, igbtclock1,igbtclock2);
endmodule
 
module freq_div(clock,rst,clock_out);
input clock,rst;
output reg clock_out;
reg [15:0] counter;
 
always @(posedge clock or negedge rst)
begin
    if(!rst)
    begin
        counter<=16'd0;
        clock_out <= 1'b0;
    end
    else
    if(counter==16'd6667)
    begin
        counter <= 16'd0;
        clock_out <= ~clock_out;
    end
    else
    begin
        counter<=counter+1;
    end
end
endmodule
 
module clock_multiplier (clock, clock1, clock2);
input clock;
output clock1, clock2;
 
assign clock1 = clock;
assign clock2 = ~clock1;
endmodule

dave_59 · Mar 6, 2014

What is your testbench supposed to instantiate as its DUT?

ads-ee · Mar 6, 2014

micktosin said:

You are instantiating the pulsegentb testbench in the testbench. The error even shows that: notgate/notgate

Also use named port mapping as opposed to positional mapping.

Instead of:

Code Verilog - [expand]
1
freq_div f1 (clock,reset,temp1);

use this:

Code Verilog - [expand]
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freq_div f1 (
  .clock   (clock),
  .rst      (reset),
  .clock_out (temp1)
);

Makes the code clearer and improves maintainability. All you have to do is have two signals swapped in a module with 50+ ports and the end result is a design that misbehaves and takes days to find the error.

micktosin · Mar 10, 2014

ads-ee said:
You are instantiating the pulsegentb testbench in the testbench. The error even shows that: notgate/notgate

Also use named port mapping as opposed to positional mapping.

Instead of:

Code Verilog - [expand]
1
freq_div f1 (clock,reset,temp1);

use this:

Code Verilog - [expand]
1 2 3 4 5
freq_div f1 ( .clock (clock), .rst (reset), .clock_out (temp1) );

Makes the code clearer and improves maintainability. All you have to do is have two signals swapped in a module with 50+ ports and the end result is a design that misbehaves and takes days to find the error.

Thanks, that was helpful. One more question, how can I introduce a dead time to the on and off times of the 'igbt_clock_gen'? For instance 750ns(on time) and 1us(off time) to my code shown below. Appreciate your help.
Test bench

Code:

module igbt_firing_tb;
 
                // Inputs
                reg clock;
                reg reset;
 
                // Outputs
                wire clock1;
                wire clock2;
                wire clock3;
                wire clock4;
 
                // Instantiate the Unit Under Test (UUT)
                igbt_clock_gen uut (
                                .clock(clock),
                                .reset(reset),
                                .clock1(clock1),
                                .clock2(clock2),
                                .clock3(clock3),
                                .clock4(clock4)
                );
 
 
                initial begin
                                // Initialize Inputs
                                clock = 0;
                                reset = 0;
 
                                // Wait 100 ns for global reset to finish
                                #100;
       
                                // Add stimulus here
                                reset = 1;
 
                end
               
                always
                                #2.5 clock = ~clock;
               
 
Endmodule

Igbt control.

Code:

///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: clk_div.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::256 FBGA>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 


module igbt_clock_gen (clock,reset,clock1,clock2,clock3,clock4);
input clock,reset;
output clock1, clock2, clock3, clock4;
wire temp1;

freq_div f1 (clock,reset,temp1);
clock_multiplier c1 (temp1,clock1,clock2,clock3,clock4);
endmodule

module freq_div(clock, rst, clock_out);
input clock,rst;
output reg clock_out;
reg [15:0] counter;

always @(posedge clock or negedge rst)
begin
	if(!rst)
	begin
		counter<=16'd0;
		clock_out <= 1'b0;
	end
	else
	if(counter==16'd6667)
	begin
		counter <= 16'd0;
		clock_out <= ~clock_out;
	end
	else
	begin
		counter<=counter+1;
	end
end

endmodule

module clock_multiplier (clock, clock1, clock2, clock3, clock4);
input clock;
output clock1, clock2, clock3, clock4;

assign clock1 = clock;
assign clock2 = ~clock1;
assign clock3 = clock1;
assign clock4 = ~clock1;

endmodule

[And it will be helpful if you can reccomend a good book on Verlog/vhdl prodramming.]

Thanks.

ads-ee · Mar 10, 2014

micktosin said:
Thanks, that was helpful. One more question, how can I introduce a dead time to the on and off times of the switching? For instance 750ns(on time) and 1us(off time) to my code shown below. Appreciate your help.

Add dead time to what? I'm not sure what you want to shut off and on. Do you mean in the freq_div module?

[And it will be helpful if you can reccomend a good book on Verlog/vhdl prodramming.]

I have the Douglas Perry "VHDL" book and the Samir Palnitkar "Verilog HDL" books, I also have this book at home https://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438 I have an old copy and the binding was garbage for the early editions so my copy is in about 100 pieces.

micktosin · Mar 10, 2014

ads-ee said:
Add dead time to what? I'm not sure what you want to shut off and on. Do you mean in the freq_div module?

I have the Douglas Perry "VHDL" book and the Samir Palnitkar "Verilog HDL" books, I also have this book at home https://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438 I have an old copy and the binding was garbage for the early editions so my copy is in about 100 pieces.

I meant 'igbt_clock_gen', sorry for the confusion. Yeah I will check that book out thanks.

ads-ee · Mar 10, 2014

igby_clock_gen only has instances of other modules. There isn't any sequential code in that module. So that still doesn't answer what you are trying to enable and disable. Is it that you want to turn the clocks on and off?

micktosin · Mar 10, 2014

ads-ee said:
igby_clock_gen only has instances of other modules. There isn't any sequential code in that module. So that still doesn't answer what you are trying to enable and disable. Is it that you want to turn the clocks on and off?

Hi, I am using it to switch 4 IGBTS, with only two transistors on at a time. I just want to include dead timing to avoid cross conduction. So for instance, when IGBT 1 & 3 is on 2 & 4 will be off respectively. After looking at the code again, I think the dead timing will be applied to the output from clock_multiplier as its the ones that leads to ouput.

Kind Regards.

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micktosin

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Code Verilog - [expand]
1 2 3	module pulsegentb(); ... pulsegentb notgate(clock, igbtclock1, igbtclock2);

Code Verilog - [expand]
1 2 3 4 5	freq_div f1 ( .clock (clock), .rst (reset), .clock_out (temp1) );

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