[SOLVED] [new] verilog operator

Status
Not open for further replies.

cloud9Z9

Newbie level 5
Joined
Dec 9, 2011
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,330
what does out = (in+1)%(1<<16); mean ?? both in and out are 16 bit busses. I understand in+1 but why % 1<<16?
 

this mean out can not exceed 2^16 = 65536. After out is 65535, the next value will be 0.
 

From a functional point of view 1<<16 is redundant because out is 16-bit, which will not exceed 655535 anyway.

Cheers,
Jim


this mean out can not exceed 2^16 = 65536. After out is 65535, the next value will be 0.
 
Last edited:
From a functional point of view 1<<16 is redundant because out is 16-bit, which will not exceed 655535 anyway.

Indeed. Although there's one subtle difference if I'm not mistaken. Just "out = (in+1)" will issue a warning since (in+1) is a 17-bit result, which is then truncated to 16-bit. The "(in+1)%(1<<16)" version is a 16-bit result, so you don't get truncation warnings during synthesis. But as you say, both result in the same functionality. Besides, personally I always do something like "out = in + 1'd1" to avoid those pesky truncation warnings and is a bit more readable than the whole modulo thing.
 
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…