[SOLVED] new type-byte_vector

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ya_montazar

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hi,
Is it standard to make a new type like this in vhdl:
Code: 
subtype byte is std_logic_vector(7 downto 0);
type byte_vector is array (natural range <>) of byte;

when I do this I have faced some unknown errors...
 

should be nothing wrong with that. Whats the errors?

NOTE: as a style guidline its usually advisiable to append _t or _type on the end of the type name, so you know its a type and not a signal/variable:

subtype byte_t is std_logic_vector(7 downto 0);
 
thank you.
for example when I make a symbol which contains some ports declared as "byte_vector" and use it in a new schematic it generates an error and when I track the error in the "vhf" file of that schematic, I see that the port which I have declared as my new type,byte_vector, declared as std_logic_vector by ISE.
it seems that the ISE does not like to face user-defined types!
 

You are apparently talking about limitations of schematic entry rather than VHDL. There should be no problems in a pure VHDL design.

Regarding ports, it's necessary to define types used in the interface in a package that is imported in all design entities using it.
 
Regarding ports, it's necessary to define types used in the interface in a package that is imported in all design entities using it.
Click to expand...
exactly I have do this.
thank you for your guide.
 

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