hello guys, i am new to libero soc, and have a problem.
when i compile the project , an error happened . it was said that "Number of CORE modules (1960) exceeds the limit (1536) of the selected device."
is that means i should change another device in order to make it work?
but the device was already chosen by my tutor. he means this project can work on well in his computer.
Which device exactly? Although I don't know how the tool counts "core modules", I presume your design is too complex to fit the device, or at least coded inefficiently.
Reducing the amount of logic involved by your design can be a way to make the design fit.
One common case where a huge a amount of undesired logic is inferred - In your design are you inferring RAMs? If yes is it being done correctly?
Reducing the amount of logic involved by your design can be a way to make the design fit.
One common case where a huge a amount of undesired logic is inferred - In your design are you inferring RAMs? If yes is it being done correctly?
Thanks for your reply. there is indeed a rams module in the project. (i don't know the accurate meaning of "infer",i‘m not a English speakers ) .
The problem has been solved after i choose the NO when i meet the warning as below. And I don't know why.
Which device exactly? Although I don't know how the tool counts "core modules", I presume your design is too complex to fit the device, or at least coded inefficiently.
@Uuumillman
"Inferring RAMs" is a commonly used technology term (of course borrowed from English language), if you are familiar with the common terminologies. Almost all FPGA vendor docu will use this term in their document!
btw - You "yes/no" dialog box solution does not throw more light in to what the problem actually was or what the tool does with your solution.
If you do not want to proceed further, you may close this thread.