aminpix
Full Member level 2
- Joined
- Sep 30, 2008
- Messages
- 120
- Helped
- 2
- Reputation
- 4
- Reaction score
- 2
- Trophy points
- 1,298
- Activity points
- 2,482
It is my first time to run DDR simulation in SIwave. I want to check my DDR3 design in SIWave (a Zynq FPGA is connected to two DDR3), but when I select the nets to run simulation, I get this error:
I have checked my PCB/layout and schematics and nothing is wrong with them. (I have checked my PCB and schematics and everything is fine. no DRC error and no disconnection)
Can anyone help me what is my mistake?
I have checked my PCB/layout and schematics and nothing is wrong with them. (I have checked my PCB and schematics and everything is fine. no DRC error and no disconnection)
Can anyone help me what is my mistake?
Last edited: