netlists and wait statement

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shizu

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Hello I'm working with fpgas and I have some basic questions:

what is a netlist? from what I've read online it's a textual representation of a schematic :thinker:

what is a back annotated netlist?

why is wait not synthesizable?

thank you!
 

Yes, a netlist is just a list of nodes and what is connected to each of them. It is only a connection list, it holds no representation of the schematic or logic diagram layout.

Back annotation is the process of automatically going through a netlist and updating it when a change has been made to the schematic. For example, if you renumbered gates/components or added/removed something, the back annotation would update the netist to reflect the new parts and their connections.

I would guess that 'wait' is a function rather than a physical attribute so it would not have connections and therefore has no place in a netlist.

Brian.
 

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