Netlist with top level subckt

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srieda

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Hello all,
I am new to cadence. I want to do the following. When I output a HSPICE netlist from Virtuoso Analog Design Environment, I am getting the netlist properly. But suppose I want to output it with the top level also extracted as a subckt, how do I do it?
Please do help me as I am stuck and need this info to proceed.

Thanks in advance..
 

Im not sure about the sadence platform, but usually you need to have a symbol for the top level to have it as a subckt in your netlist.
So create a symbol for the top level and then try to netlist it out. The Mentor platform provides an option to netlist it out as a subckt if you have a symbol. Check for such an option in cadence and you are done.

--cmos_dude
 

That is precisely what I am not able to find out. I was using some other tool previously where this option was always provided when I was outputting a netlist. But here, in cadence I do not know how to do it.

Please somebody help me out...
 

What do you need? To extract netlist from layout for post-sim? You want hierarchy netlist extraction?
 

leo_o2 said:
What do you need? To extract netlist from layout for post-sim? You want hierarchy netlist extraction?
Click to expand...

I want hierarchy netlist extraction from schematic... not layout.. I want it so that I can do scripting to generate the pin list on the top-level.
 

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