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when i use fingers for transistor, there is a mismatch error b/w Layout vs Schematic. In inverter circuit, i used 2 fingers for both nmos nd pmos. after completing the layout design, during LVS check, mismatch error appeared. how to resolve this?
From the output you can't say that this is not a real
hookup error. Intentions don't enter into it.
You might look into how the PDK rules support multi-
finger devices, the "permute parallel" into a single
device might be turned off or unsupported, or the
PDK may have multiple CDF fields that indicate
fingers and you used the wrong one, or something.
If I were you I'd begin with chasing all those
unmatched nets and instances and "eyeball LVS"
what you see vs what you show on your schematic.
But you could also check with whoever produced
the PDK, about the approved way of representing
multifinger devices.
As a fallback, instantiate one FET per finger and
wire it up in the schematic as it truly is laid out.
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