Net delay on port in Design Compiler topographical mode

Deal all,

Current I find that there is net delay between the PAD and port after applying Design Compiler topographical mode.
However, this net delay can not be ignored and it only appear in topographical mode with given DEF file.
Have you ever this situation ?

The report is like following case:
...
A_top_inst/uF/f_dat_oe_2 (A_top) 0.00 1.83 f 1.08
A_top_inst/F_DATO_OE_2 (A_top) 0.00 1.83 f 1.08
pad_top/fdd2_oe (pad_top) 0.00 1.83 f 1.08
pad_top/PAD86/IO (PIOHSR_PU) 8.54 * 10.37 f 1.65 ~
pad_top/FDD2 (pad_top) 0.00 10.37 f 1.65
FDD2 (inout) 0.23 * 10.60 f 1.65
data arrival time 10.60

max_delay 10.40 10.40
output external delay 0.00 10.40
data required time 10.40
------------------------------------------------------------------------------------
data required time 10.40
data arrival time -10.60
------------------------------------------------------------------------------------
slack (VIOLATED) -0.20


I have issued command set_load to model the real chip.
And I guess the DCT will also calculate the RC induced by wire connection.
Therefore, this causes the net delay on port.

But I just face this issue in the first time.
I don't know whether it indeed exist or just a bug.
Please help me with your experience.

Many thanks.
Best Regards.

PoLo