using the following to "test" your code in Modelsim 10.1b. It ran fine for the 256 clock cycles.
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| module test2;
reg [3:0] in [0:2][0:2];
reg [3:0] n;
reg [7:0] hist [0:15];
reg [7:0] count = 8'b0;
reg clk;
integer i,j;
initial begin
clk = 1'b0;
hist[ 0] = 8'b0;
hist[ 1] = 8'b0;
hist[ 2] = 8'b0;
hist[ 3] = 8'b0;
hist[ 4] = 8'b0;
hist[ 5] = 8'b0;
hist[ 6] = 8'b0;
hist[ 7] = 8'b0;
hist[ 8] = 8'b0;
hist[ 9] = 8'b0;
hist[10] = 8'b0;
hist[11] = 8'b0;
hist[12] = 8'b0;
hist[13] = 8'b0;
hist[14] = 8'b0;
hist[15] = 8'b0;
forever begin
clk = 1'b0;
#5;
clk = 1'b1;
#5;
end
end
// generate test data
always @ (posedge clk) begin
in[0][0] <= $random;
in[0][1] <= $random;
in[0][2] <= $random;
in[1][0] <= $random;
in[1][1] <= $random;
in[1][2] <= $random;
in[2][0] <= $random;
in[2][1] <= $random;
in[2][2] <= $random;
count <= count + 8'b1;
if ( &count ) $stop;
end
always @(posedge clk) begin
for (i=0;i<=2;i=i+1) begin
for (j=0;j<=2;j=j+1) begin
n <= in[i][j];
hist[n] <= hist[n]+1'b1;
end
end
end
endmodule |
I'm assuming this is non-synthesizable testbench code, because there are blocking statements in the always block. I attempted to synthesize the code to see what those blocking statements would generate but the results didn't make much sense. I used ISE 13.3, probably should have used Quartus II 12 as I've had issues with ISE RTL schematic generation.