[SOLVED] Negative value in Verilog

Status
Not open for further replies.

sobella1923

Newbie level 4
Joined
Jun 17, 2013
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
43
is it possible to assign a negative value to a reg in verilog. I have

reg [11:0] ptr;

instead of 0 i want to initialize this vector with -1

ptr=-1-1-1-1-1-1-1-1-1-1-1-1

how can i do that???
 

I have a hard time believing that. How did you come to that conclusion?

- - - Updated - - -

Also, you did notice the difference between a vector and a number, right?

I just gave you a single 8-bit signed number. No need to add the extra confusion of a vector of signed numbers if the problem of the day is "How do I work with signed numbers in verilog".

- - - Updated - - -

Some examples using signed: http://www.asic-world.com/verilog/verilog2k1.html
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…