Negative Timing Constraint Algorithm

[Yuya_O]

I can't understand Negative Timing Constraint Algorithm in manual of modelsim. I get the meaning that setup hold timing is become negative due to latency by parasitic components. But I can't get how I deal and think about it.

 

[kaz1]

I can't understand Negative Timing Constraint Algorithm in manual of modelsim. I get the meaning that setup hold timing is become negative due to latency by parasitic components. But I can't get how I deal and think about it.

If it is in the context of timing closure of setup/hold:
At flip's internal sampling point both setup and hold must be positive relative to clock edge arriving there (sampling window).

At flip's ports perspective a delay between data port (D) and clock port(clk) will shift the timing window then negative setup or hold can occur. For example flips in FPGAs may have negative hold meaning the vendors have added some internal delay to data path relative to clock path inside flip. Timing closure (Fmax) targets flip's ports perspective.

 

[tepalia02]

Negative timing constraints arise when the path delay from a source to a destination is shorter than the required setup or hold time for the destination signal. This can happen when there is a significant amount of latency introduced by parasitic components such as capacitance or inductance in the path.

To deal with negative timing constraints, you will need to adjust the timing constraints for the affected paths to account for the additional latency. Here are some general steps you can follow:

1. Identify the signals that are affected by negative timing constraints. You can use timing reports from synthesis or static timing analysis to identify these signals.
2. Determine the amount of additional latency that needs to be added to the affected signals to meet the setup and hold time requirements. This can be done by simulating the design with parasitic delay information or using physical timing analysis tools.
3. Add a negative timing constraint to the affected signals to account for the additional latency. The negative timing constraint should be equal to the amount of additional latency that needs to be added.

For example, if the path from a source signal to a destination signal has a required setup time of 1 ns and a path delay of -0.5 ns, you would need to add a negative timing constraint of 1.5 ns to the destination signal to account for the additional latency.