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Negative Port Impedance CST Studio ?

Max01800

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I'm trying to simulate a simple microstrip line like in the photo. I'm using discrete port as you can see.

1729326083909.png


In the tree options there is the section of Discrete port --> Impedances.
1729327581779.png

For Port 2 [1] the real part of the impedance is -50 Ohm
1729326214372.png


since Z=V/I, I suppose that it's negative because the current and voltage in frequency domain have opposite sign on port 2 [1].

1729326630928.png


1729326659856.png


I've seen that if the two discrete ports are in opposite verse the current sign doesn't change while the voltage sign does change.
1729327507051.png
1729327392070.png

if the discrete ports have the same verse then the current sign does change while the voltage's sign doesn't change

1729327324128.png
1729327355855.png


this doesn't make sense to me. The real part should be positive.
 
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if the discrete ports have the same verse then the current sign does change while the voltage's sign doesn't change

Makes sense, because for port 1 excitation, the current goes OUT OF port 1 (source) and goes INTO port 2 (sink)
Make sure both ports have the same direction, i.e. the port arrow goes down on both ports, or up on both ports, but not mixed.
 
Makes sense, because for port 1 excitation, the current goes OUT OF port 1 (source) and goes INTO port 2 (sink)
Make sure both ports have the same direction, i.e. the port arrow goes down on both ports, or up on both ports, but not mixed.
And is this also the reason why Re{Z(port 2[1])}<0 ?
 
I'm not sure, but if the voltage measurement has wrong sign this might be the reason. I user other EM tools, so I don't know what other side effects the mixed port direction has in CST.
the problem is not the mixed port direction. Even when I use both ports with the same direction I get Re{Z(port 2[1])}<0. But if you say that it does make sense that the current on port 2 has opposite sign I think that is the reason.
 

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