Negative Latch in Clock Gating

[identical]

Why do we need a negative latch in gating the clock. I understand why it is needed (to hold the enable until clock goes low) but why can't positive latch do the trick too?

 

[jt_eaton]

The enable signal changes on the rising clock edge and is latched during the clock low time so it is set up and stable for the next clock pulse.

If you used a positive latch then the same clock that changed the enable would be gated out immediately and would be one pulse early.

The difference is that a negative latch places the output clock one and gate delay after the input clock so that clock tree synthesis can
manage its insertion delay.

A positive latch places the output clock one clock to Q time plus one and gate delay later and is a lot messier.

John Eaton

 

[identical]

The enable signal changes on the rising clock edge and is latched during the clock low time so it is set up and stable for the next clock pulse.

If you used a positive latch then the same clock that changed the enable would be gated out immediately and would be one pulse early.

The difference is that a negative latch places the output clock one and gate delay after the input clock so that clock tree synthesis can
manage its insertion delay.

A positive latch places the output clock one clock to Q time plus one and gate delay later and is a lot messier.

John Eaton

I still find it hard to grasp for some reason. If it was one pulse early wouldn't that ease timing?

 

[artmalik]

Most of the clock gaters are designed to keep the output clock to VSS when the enable signal is 0. You can do the opposite as well but it is not common. the negative latch is required because you want the output clock to 0 when the clock gater is off.

 

[morris_mano]

If the CGC enable, which may come from combinational logic, goes high in between when the clock signal is high, it may potentially clip the clock pulse output of CGC if we use positive latch in the CGC instead of negative latch. This may produce variable clock pulse width.

 

[identical]

If the CGC enable, which may come from combinational logic, goes high in between when the clock signal is high, it may potentially clip the clock pulse output of CGC if we use positive latch in the CGC instead of negative latch. This may produce variable clock pulse width.

But wouldn't the latch hold the enable until the next clock edge comes?

 

[morris_mano]

But wouldn't the latch hold the enable until the next clock edge comes?

**broken link removed**

The original CGC cell is shown in the diagram above. If you replace with positive latch, during clock high period, the latch is transparent, and the clock output of cgc depends on enable signal. Therefore, if enable goes high in between clock high period, the AND gate after latch clips the clock pulse.