sisari
Junior Member level 3
sdf negative timing
After synthesizing a VHDL design with Synopsys DC I get negative values
in the SDF file for HOLD check of the FFs . I am doing simulations with Modelsim and the simulator uses those negative HOLD values by substracting them from the setup time ( If i deliberately make a setup violation closer to the clock edge the simulator does not report any error ).
Anyone can make me understand what neagtive values for the HOLD are intended for ?
Thanks!
After synthesizing a VHDL design with Synopsys DC I get negative values
in the SDF file for HOLD check of the FFs . I am doing simulations with Modelsim and the simulator uses those negative HOLD values by substracting them from the setup time ( If i deliberately make a setup violation closer to the clock edge the simulator does not report any error ).
Anyone can make me understand what neagtive values for the HOLD are intended for ?
Thanks!
