negative feedback question (current mirror)

[evilguy]

can someone give brief idea how to design the comparator in this circuit. All i know, this circuit use negative feedback to assure drain voltage for both transistor (M1 and M2) have the same potential. This is essential for perfect mirror so that IdM1=IdM2. how this circuit respon and correct the node voltage? i've tried to read the negative feedback theory but i can't relate the theory with this circuit. thanks

 

[DenisMark]

It isn't comparator, it's an amplifier (in many cases it's OTA or simple CS stage). Yes, it serves to make drain-source potentials of M1,M2 equal for perfect matching their drain currents. Also this ckt boost ouput resistance about Rout~A/gds2, A - gain of amplifier, gds2 - conductance of M2.
This circuit is used very seldom, usually cascode current mirror, because negative feedback amplifier+M3 may suffer from stability issue. U can read about ckt like this in Razavi's or Allen's books. If u need some briefing, OTA cell must include nmos diff. pair (because CM range close to positive rail), folder cascode or active current mirrors configuration. During simulation it's necessary check stability for feedback.

 

[evilguy]

thanks... how to assure the stability? if vin- for the opamp is not equal to vin+ the opamp output should control gate voltage of M3 to sink more current so that vin- will approach vin+. The system is in stable state when vin+ = vin-. I understand the system. But i dont know how to design the opamp to do this kind of work. What is the spec for the opamp should i design?

 

[DenisMark]

U've just explain the principle of the negative feedback operation, but stability means a something more. The ckt is stabile when at frequency where open loop gain = 0dB the additional phase shift is less than 180deg. This means that negative feedback never becomes positive.
See example of OTA for ur ckt. U don't know ur goal. If Ibias of ur ckt is constant, u won't need large bandwidth for OTA and u'll can choose small bias current for it. Gain of OTA is depended from desired Rout value. If u need better PSRR use cascoding (e.g. folder cascode OTA).

 

[surianova]

can someone give brief idea how to design the comparator in this circuit. All i know, this circuit use negative feedback to assure drain voltage for both transistor (M1 and M2) have the same potential. This is essential for perfect mirror so that IdM1=IdM2. how this circuit respon and correct the node voltage? i've tried to read the negative feedback theory but i can't relate the theory with this circuit. thanks

Actually this should not work bcoz it is not negative feedback... you shd connect the drain to the +ve terminal of opamp to make it work...

 

[evilguy]

can you eloborate further why this wont work? some equation might be usefull. the 1st stage of opamp usually differential amplifier. is it really concern which input is +ve or -ve? either one can be +ve and the other should be -ve. correct me if i'm wrong.

 

[DenisMark]

Don't worry about. Surianova is mistaken.
M3 is a common drain stage, it don't invert phase.

 

[surianova]

Don't worry about. Surianova is mistaken.
M3 is a common drain stage, it don't invert phase.[/quo

yes, it is truth.. I thought is a Nmos. There is no inversion there.

 

[evilguy]

referring to my attachment above, if i want to desingn the opamp, what load capacitance should i put for the opamp to drive.

 

[RickLi]

I think when designing the oamp, maybe you can consider the source follower as the output stage of the opamp, and the current mirror is its bias circuit, so no more load capacitance is needed.

Please correct me if I made some mistakes.

 

[evilguy]

@RickLi
can you explain why we dont need the load capacitance if the output stage is source follower?

 

[DenisMark]

For above ckt the load capacitance is only needed to resolve stability issue. The pole at in- input is high frequency because M3 forms CD stage. The unity gain frequency of OTA is UGF=Gm/Cload, Gm - transconductance of input diff.pair, Cload - load capacitance of OTA. Dominant pole (Bandwidth) is pd=-1/(Rout*Cload). Gain is A=Gm*Rout.
In present case Cload=CgateM3, if Cload is small, parasitics poles in neg. loop may cause an instability. Ur goal is one pole system and location of this parasitics poles about 2 times above UGF. That is why u need to decrease UGF and the addititional Cload or small Gm is requered.
Easy, Cload isn't requered if CgateM3 is big, or Gm is small.

 

[RickLi]

Originally the load is the gate capacitance of M3.

But if you include M3, the source follower, into the OPamp, the output (source of M3) is directly feedback to vin-. The question is to design the unity-gain buffer formed by the OPamp, with no more load to drive.

How do you think?

 

[evilguy]

The question is to design the unity-gain buffer formed by the OPamp, with no more load to drive.

i dont get the meaning. hope you can explain it.

i've roughly design the opamp. i use simple two stage opamp and i use miller compensation technique to get 60° phase margin because according to allen book, 60° phase margin is desirable. I've added active resistor, M4 to the circuit so that i can print the output current. the output is shown in the figure. my question is

1. As we can see from the figure, the system need like 50µs to stable. In theory, how we can speed up the time for the system to reach steady state? Perhaps by redesign the opamp for larger bandwidth?

2. The 2nd figure shown the delta current, mean IM2-IM1. It show slide mismatch about 7nA. What i can observ from the output file simulation, the drain voltage for M1 and M2 are identical. so how this mistmatch occur? in theory, if vgs,vds, and ratio is identical, these two transistors should have same drain current.

3.At 1st, the mismatch is large about 0.2µA. After i resize the ratio of M3 and M4 to larger value, the mistmatch become lower to 7nA. how the sizing of these transistors affect the mistmatch. please note that when i resize these transistors, the drain voltage for M2 remain unchange when the circuit reach steady state.

hope somebody can clear these question for me.

 

[RickLi]

I meant, if the source follower M3 is included in the opamp, and M1 & M2 are the bias circuit, the output of the opamp is the source of M3, which only drives vin-. (M4 seems can be negligible when analysing stability.)

1. I think you need larger loop bandwidth.

2. 7nA is quite a small amount. Though vin+ and vin- are virtually shorted, there still can be some small voltage difference between them, which can cause a small mismatch between the IMs.

3. I don't understand your question. I think maybe you can find out the answer by checking the operation region of each device.

 

[evilguy]

3. I don't understand your question. I think maybe you can find out the answer by checking the operation region of each device.

what i meant is at 1st i biased M3 and M4 in active region. after I simulated the circuit, i found out that the mismatch is 0.1µA. for example, IM1=22µA and IM2 is 22.1µA. the ratio for M3=M4=5 (this value for example only). So i did some experiment, I enlarged the ratio for M3 and M4 to 100. then i simulated the circuit and found out the mismatch is 7nA (IM1=22µA and IM2=22.007µA). My question, is why the mismatch reduced when I enlarge the ratio of M3 and M4 to 100?

one of the odd thing is, the operating region for M3 and M4 is not in active region anymore when i enlarge their ratio to 100. i suspect the region is in subtreshold region since their vgs<Vt

1. I think you need larger loop bandwidth.

How to measure loop bandwidth of the opamp? Is this bandwidth similar to unity gain bandwidth?

 

[RickLi]

1. I think when the ratio is larger, the difference between vin+ and vin- gets smaller, maybe because of bias condition, and it makes the matching better.

2. Yes, for an opamp with vout connected to vin-, the loop gain is (roughly) the open loop gain of the opamp. I said "roughly" because the input capacitance of vin- should be considered for accurate loop gain definition.

 

[evilguy]

see my result above, after the system in steady state, IM2 is almost equal to IM1. however the current seem ocillate about 100kHz. is this acceptable? why the current cannot get straight line without ocillation? is my negative feedback is correct?

from my reading, negative feedback can switch to positive feedback if not compensate well. The result of positive feedback is the output will ocillate. so, my feedback is positive?

 

[surianova]

3. I don't understand your question. I think maybe you can find out the answer by checking the operation region of each device.

what i meant is at 1st i biased M3 and M4 in active region. after I simulated the circuit, i found out that the mismatch is 0.1µA. for example, IM1=22µA and IM2 is 22.1µA. the ratio for M3=M4=5 (this value for example only). So i did some experiment, I enlarged the ratio for M3 and M4 to 100. then i simulated the circuit and found out the mismatch is 7nA (IM1=22µA and IM2=22.007µA). My question, is why the mismatch reduced when I enlarge the ratio of M3 and M4 to 100?

one of the odd thing is, the operating region for M3 and M4 is not in active region anymore when i enlarge their ratio to 100. i suspect the region is in subtreshold region since their vgs<Vt

1. I think you need larger loop bandwidth.

How to measure loop bandwidth of the opamp? Is this bandwidth similar to unity gain bandwidth?

I think the mismatch current become less when u increase the size of M3 and M4 is due the loop gain of the ngative feedback have been increased. When u increase the size of M3, actually u increase the gm of M3 which is contribute to overall negative feedback loop gain. Although M3 is source follower, normally need to have gain around 0.8... maybe before u increase the size of M3, the gain is around 0.6. If the loop gain is high, there is less error between V+ and V-.

For fast settiing time, of course u need fast badwidth opamp, u just measure the badwidth 3 dB below the gain.