hi...,why is negative edge triggering more power saving than positive edge triggering... i came across that it is mainly because -ve edge triggering only does discharging operation while the +ve edge triggering charges the capacitance....could some one explain what are the transistors that are involved in this charging and dischaging... and why these operations take place...
Can you show the particular circuit which saves more power on negative edge triggering FlipFlop?
As far as I know, there should be no difference regarding to positive/negative triggering F.F.
hi lordsathish,as far as i know,for the inverter,when the input is low level,PMOS is on and NMOS is off
the power is 1/2fCV^2
when input is high : PMOS is off and NMOS is on
the power is also 1/2fCV^2
in one clock cycle ,the total power is fCV^2
can you give me an example which saves power on negative edge triggering FF.
BR. varkylin
Hi all,
You're right lordsathish concerning the power. Another point to note is that, in practice, the negative edge is harder to detect than the positive edge and require in certain cases additional circuitry. That's why positive triggering still better.
Hi,
negative triggering will trigger a ptype devive and hence less consume less power. But i am not clear why positive triggering is better? Masterpiece could you please elaborate?