Needed: High reisstance Poly AMI 0.5um SPice model file

[srivatsan]

poly resistor spice model

I need the SPICE model for high resistance poly spice model file. Thanks in adavcen.

srivats

 

[Vamsi Mocherla]

metal 1 resistor model mosis

Try the MOSIS website. May be you will get it there. I guess 0.5u is a pretty old process

 

[srivatsan]

0.5um model

WEll, I had a good look at the website well before i made this request.

it seems that you need to replace the extracted stuff with resistor statement itself. what i am worried is whether it will actually be fabricated, in the manner that I wanted. i had fabricated one before, but it was digital (ALU, FIR). not so sure about op-amp. just waiting to see whether anyone has actually done some of which they had designed.

thanks to vamsi. if you can get any model specifically let me know..

srivats

 

[Vamsi Mocherla]

0.5um technology file

Dear Vatsan,

We definately use Poly resistors with Salicide block (which causes the high resistance). I have seen foundry runs for more than 3 LDOs and a couple of DACs and there i have used the resistors. Well, mostly all CMOS processes should support resistors because, they are not any extra layer. I will see if I can get any of the resistor models for 0.5 micron AMI process

 

[srivatsan]

unimplemented control card - error spice

Dear Vamsi:
Nice to know that there is someone who has fabricated what they design. I do know that they have resistors in the AMI 0.5 um process. actually, i have pasted the statement after the ext2spice -f spice3 -t! -t# <filename.ext>; which contains the resistance.

M1000 Vdd c_102_58 a_58_42 a_108_43 phrResistor W=14 L=44
+AD=0 ......

This means that the resistor is extracted as "Special MOSFET", with one end Vdd and the other end a_58_42; this encompasses W vs L area.

Now if I can get the model for phrResistor (which has to be as simple as L*Rsquare/W), then it should work .... .. or I am not able to write a simple model file, i dont know the reason.

Now I hope the above statements are clear.

If you can get it... I would really appreciate it..
thanks.
srivatsan

 

[Vamsi Mocherla]

unimplemented control card spice

Dear Vatsan,

I have a model file for resistors in some of the SPICE decks we have. Look at how they have done that. Please look into each model a foundry normally has. Ours is a CMOS single well process.

***** Resistor Models *****
.lib RES

* nw= NWELL resistor under STI
.subckt nw n1 n2 l=length w=width
.param rsh=1100 tc1=3.48E-03 tc2=1.15E-05 vc1=6.96E-03 vc2=-2.75E-05 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends nw

* rnps= N+ diffusion resistor salicided
.subckt rnps n1 n2 l=length w=width
.param rsh=4.5 tc1=2.88E-03 tc2=-4.36E-07 vc1=-2.33E-04 vc2=1.29E-04 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rnps

* rpps= P+ diffusion resistor salicided
.subckt rpps n1 n2 l=length w=width
.param rsh=4.0 tc1=3.62E-03 tc2=-5.05E-07 vc1=-1.73E-03 vc2=1.37E-03 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rpps

* rnpns= N+ Active resistor non-salicided
.SUBCKT rnpns 1 2 l=length w=width contact=1
.param rc=6.4
.param rsh=65 dw=0.047u t='temper' trs1=1.55E-03 trs2=-3.51E-07 vrs1=4.00E-04 vrs2=-4.00E-04
.param rint=27.608u trt1=5.22E-03 trt2=-2.77E-05 vrt1=-2.68E-03 vrt2=2.18E-02
.param trsh='1.0+trs1*(t-25.0)+trs2*(t-25)*(t-25)'
.param trint='1.0+trt1*(t-25.0)+trt2*(t-25)*(t-25)'
rc1 1 a 'rc/contact'
rend1 a b 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(a,b))+vrt2*v(a,b)*v(a,b))'
rp b c 'rsh*(l/(w-dw))*trsh*(1.0+vrs1*abs(v(b,c))+vrs2*v(b,c)*v(b,c))'
rend2 c d 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(c,d))+vrt2*v(c,d)*v(c,d))'
rc2 d 2 'rc/contact'
.ENDS rnpns

* rppns= P+ Active resistor non-salicided
.SUBCKT rppns 1 2 l=length w=width contact=1
.param rc=5.4
.param rsh=140 dw=0.065u t='temper' trs1=1.44E-03 trs2=3.67E-07 vrs1=5.97E-03 vrs2=-1.10E-03
.param rint=190.66u trt1=-2.79e-03 trt2=5.47E-06 vrt1=-1.17E-01 vrt2=1.50E-02
.param trsh='1.0+trs1*(t-25.0)+trs2*(t-25)*(t-25)'
.param trint='1.0+trt1*(t-25.0)+trt2*(t-25)*(t-25)'
rc1 1 a 'rc/contact'
rend1 a b 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(a,b))+vrt2*v(a,b)*v(a,b))'
rp b c 'rsh*(l/(w-dw))*trsh*(1.0+vrs1*abs(v(b,c))+vrs2*v(b,c)*v(b,c))'
rend2 c d 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(c,d))+vrt2*v(c,d)*v(c,d))'
rc2 d 2 'rc/contact'
.ENDS rppns

* rngps= N+ Poly resistor salicided
.subckt rngps n1 n2 l=length w=width
.param rsh=5.0 tc1=3.22E-03 tc2=-6.61E-07 vc1=-2.00E-04 vc2=9.52E-04 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rngps

* rpgps= P+ Poly resistor salicided
.subckt rpgps n1 n2 l=length w=width
.param rsh=5.0 tc1=3.46E-03 tc2=-5.77E-07 vc1=-2.88E-03 vc2=3.13E-03 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rpgps

* rngpns= N+ Poly resistor non-salicided
.SUBCKT rngpns 1 2 l=length w=width contact=1
.param rc=4.2
.param rsh=190 dw=0.062u t='temper' trs1=-8.99E-04 trs2=2.07E-06 vrs1=-1.34E-04 vrs2=8.71e-04
.param rint=48.03u trt1=9.68E-04 trt2=-3.50E-05 vrt1=-3.11E-01 vrt2=-2.31E-02
.param trsh='1.0+trs1*(t-25.0)+trs2*(t-25)*(t-25)'
.param trint='1.0+trt1*(t-25.0)+trt2*(t-25)*(t-25)'
rc1 1 a 'rc/contact'
rend1 a b 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(a,b))+vrt2*v(a,b)*v(a,b))'
rp b c 'rsh*(l/(w-dw))*trsh*(1.0+vrs1*abs(v(b,c))+vrs2*v(b,c)*v(b,c))'
rend2 c d 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(c,d))+vrt2*v(c,d)*v(c,d))'
rc2 d 2 'rc/contact'
.ENDS rngpns

* rpgpns= P+ Poly resistor non-salicided
.SUBCKT rpgpns 1 2 l=length w=width contact=1
.param rc=4
.param rsh=160 dw=0.074u t='temper' trs1=7.42E-04 trs2=1.13E-06 vrs1=1.13E-04 vrs2=-7.51E-04
.param rint=124.134u trt1=-1.16E-03 trt2=-1.19E-06 vrt1=-5.59E-04 vrt2=4.61E-02
.param trsh='1.0+trs1*(t-25.0)+trs2*(t-25)*(t-25)'
.param trint='1.0+trt1*(t-25.0)+trt2*(t-25)*(t-25)'
rc1 1 a 'rc/contact'
rend1 a b 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(a,b))+vrt2*v(a,b)*v(a,b))'
rp b c 'rsh*(l/(w-dw))*trsh*(1.0+vrs1*abs(v(b,c))+vrs2*v(b,c)*v(b,c))'
rend2 c d 'rint/(w-dw)*trint*(1.0+vrt1*abs(v(c,d))+vrt2*v(c,d)*v(c,d))'
rc2 d 2 'rc/contact'
.ENDS rpgpns

* rm1= Metal 1 resistor
.subckt rm1 n1 n2 l=length w=width
.param rsh=0.08 tc1=3.37E-03 tc2=9.00E-07 vc1=0 vc2=0 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rm1

* rm2= Metal 2 resistor
.subckt rm2 n1 n2 l=length w=width
.param rsh=0.06 tc1=2.66E-03 tc2=3.83E-06 vc1=0 vc2=0 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rm2

* rm3= Metal 3 resistor
.subckt rm3 n1 n2 l=length w=width
.param rsh=0.06 tc1=2.66E-03 tc2=3.83E-06 vc1=0 vc2=0 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rm3

* rm4= Metal 4 resistor
.subckt rm4 n1 n2 l=length w=width
.param rsh=0.06 tc1=2.66E-03 tc2=3.83E-06 vc1=0 vc2=0 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rm4

* rm5= Metal 5 resistor
.subckt rm5 n1 n2 l=length w=width
.param rsh=0.04 tc1=3.68E-03 tc2=-1.46E-06 vc1=0 vc2=0 t='temper'
.param tpar='1.0+tc1*(t-25.0)+tc2*(t-25.0)*(t-25.0)'
r1 n1 n2 'rsh*(l/w)*(1+vc1*abs(v(n2,n1))+vc2*v(n2,n1)*v(n2,n1))*tpar'
.ends rm5

.endl RES

 

[srivatsan]

0.5u ami

Dear Vamsi:
Thanks man.. 8) I think I get some idea here. Is there a way you can get me the instantiation of those models.... like

x123 1 2 l=2u w=3u nw

or something similar.. just to verify the way to instantiate it..

I will let you know how to get that going and hopefully others in this forum can get a better view of resistors....

Regards,
srivats

 

[Vamsi Mocherla]

0.5um hspice model

What you have written is perfectly right. Mostly the instantiation is as follows

XRES1 1 0 RPGPNS L=30u W=2u

In case you want to have mutliple fingers

XRES2 1 0 RPGPNS L=6u W=2u M=5

 

[srivatsan]

Dear Vamsi,
I tried it.. I think I am making a small mistake...

The following is the statement that appears after using "ext2spice" command:

m1000 nRb c_n237_n48 Vdd Gnd phrResistor w=4.2u l=15u
+ ad=0p pd=0u as=0p ps=0u

Then after making changes and adding the subcircuit statement.. it becomes:

x1000 nRb c_n237_n48 Vdd GND phrResistor w=4.2u l=15u
.subckt phrResistor d g s b w=width l=length
.param rsheet=1120
rbias d s 'rsheet*(l/w)'
rd1 g d 0
rd2 b 0 0
.ends phrResistor


But it does not work at all. I am not able to spot the problem.

the following are debugs I tried: to both rd1 rd2... i had quotes to 0 value. it didnt work.

Can you spot it? Let me know. thanks.
srivatsan

 

[Vamsi Mocherla]

Try and put

rd1 g d 0.00001
rd2 b 0 very high

May be there is some problem because of 0 values. Do not comment them. Or the problem could be with the type of resistor here. Connect b to VDD and invert the source and drain connections at the XCall level

 

[srivatsan]

Dear Vamsi:
Instead of working with b and g nodes; I removed them and made them see like a two terminal subcircuit. IF this works, it wont take time to put the other two nodes. Hence the subcircuit contains only d and s nodes.

It results in the following statements.

*m1000 Out c_n40_37 Vdd Gnd phrResistor w=5.7u l=21.6u
*+ ad=0p pd=0u as=0p ps=0u
x1000 Out Vdd rphrResistor
*w=5.7u l=57.0u

.subckt rphrResistor d s
.param w=5.7e-6 l=57.0e-6 rsquare=1120
rbias d s 'rsquare*l/w'
.ends rphrResistor

Note: I have included the asterik statements so that you can see the way I had proceeded.

This results in the following error:

.param w=5.7u l=57.0 rsquare=1120
unimplemented control card - error


Another approach that I took was: the following are the statements

x1000 Out Vdd rphrResistor w=5.7u l=57.0u

.subckt rphrResistor d s rphrResistor w=width l=length
.param rsquare=1120
rbias d s 'rsquare*l/w'
.ends rphrResistor

the error associated with it is:

Error: unknown subckt x1000 out Vdd .......

I kinda struck up here. Of course if I eliminated the l and w and just put 10e3 for rbias it works.... (within quotes).

See if you can help me... thanks.
Srivats

 

[Vamsi Mocherla]

dear vatsan,

I used your deck and gave a dummy run for ac and OP analysis. I am able to run the file. And seemly I am not seeing any error.

The following is your spice file

************************************************************
*m1000 Out c_n40_37 Vdd Gnd phrResistor w=5.7u l=21.6u
*+ ad=0p pd=0u as=0p ps=0u
x1000 Out Vdd rphrResistor
*w=5.7u l=57.0u

.subckt rphrResistor d s
.param w=5.7e-6 l=57.0e-6 rsquare=1120
rbias d s 'rsquare*l/w'
.ends rphrResistor

VDD vdd 0 5V ac 1V
CL Out 0 1p

.op
.ac dec 1 100M 10
.end

This is the result I have got for the resistor value from the spice .LIS file, which is correct value as per the calculations

r value 11.2000k


Case II
=====
I have also exported the data for length and width. Please follow this .LIS file for full details

Init: hspice initialization file: C:\synopsys\Hspice2003.03\hspice.ini
* hspice.ini
*
* use ascii only for initial pc hspice release
*
.option post = 2
*m1000 out c_n40_37 vdd gnd phrresistor w=5.7u l=21.6u
*+ ad=0p pd=0u as=0p ps=0u
x1000 out vdd rphrresistor length=57u width=5.7u
*w=5.7u l=57.0u

.subckt rphrresistor d s
.param l=length w=width rsquare=1120
rbias d s 'rsquare*l/w'
.ends rphrresistor

vdd vdd 0 5v ac 1v
cl out 0 1p

.op
.ac dec 10 1 100meg
.end
1 ****** HSPICE -- U-2003.03 (20030106) 20:51:24 03/03/2005 pcnt
******
************************************************************
****** circuit name directory
******
circuit number to circuit name directory
number circuitname definition multiplier
0 main circuit
1 x1000. rphrresistor 1.00
Opening plot unit= 79
file=c:\proj\spice\restest.pa0

1 ****** HSPICE -- U-2003.03 (20030106) 20:51:24 03/03/2005 pcnt
******
************************************************************
****** operating point information tnom= 25.000 temp= 25.000
******
***** operating point status is all simulation time is 0.
node =voltage node =voltage

+0ut = 5.0000 0:vdd = 5.0000


**** voltage sources

subckt
element 0:vdd
volts 5.0000
current 0.
power 0.


total voltage source power dissipation= 0. watts

**** resistors

subckt x1000
element 1:rbias
r value 11.2000k
v drop 0.
current 0.
power 0.

Opening plot unit= 79
file=c:\proj\spice\restest.ac0


***** job concluded
1 ****** HSPICE -- U-2003.03 (20030106) 20:51:24 03/03/2005 pcnt
******
************************************************************
****** job statistics summary tnom= 25.000 temp= 25.000
******

total memory used 154 kbytes

# nodes = 3 # elements= 3
# diodes= 0 # bjts = 0 # jfets = 0 # mosfets = 0

analysis time # points tot. iter conv.iter

op point 0.04 1 4
ac analysis 0.06 81 81
readin 0.00
errchk 0.02
setup 0.09
output 0.00
total cpu time 0.20 seconds
job started at 20:51:24 03/03/2005
job ended at 20:51:35 03/03/2005


lic: Release hspicewin token(s)

 

[srivatsan]

OH Boy!!!! I will get back to you with the underlaying problem with my NGSpice simulator..

Wait a mintue: You used HSPICE .. I used NGSpice... Is there a difference between the simulator syntax?? I will be damned if it is so....

Thanks Vamsi...

Srivatsan

 

[Vamsi Mocherla]

Dear Vatsan,

I think there could be one. But this is a very simple sub-circuit to be missed. Please check into that.

 

[srivatsan]

Dear Vamsi:
I have attached my spice code for Start up with current reference circuit. Can you please execute it using HSPICE and let me know the value of i(VD) by plotting it. Thanks....
Regards,
srivatsan

 

[Vamsi Mocherla]

Dear Vatsan,

I have plotted from your SPICE file blindly. I am getting a current in the order of few pA. I am attaching the pdf fo the result

 

[Vamsi Mocherla]

Dear Vatsan,

When I am trying to run a dc analysis- sweeping the VDD values, I am getting very huge currents at the initial condition. In the transient ramp test(for VDD), the circuit is not converging. Are you sure that there is no problem in the file you have sent to me? Because, these values are rare, I am curious about the netlist. Can you update the schematic for me?

 

[srivatsan]

Dear Vamsi,
Well they are from the layout; I am not able to printscreen it and save it as a jpeg for some reason... well here is the spic file again.. i am defintiely not suprised because my circuit gives 7uA when simulated in spectre and correct stuff in ngspice. Since yours is HSPICE, it should actually corroborate with mine. Please simulate the following one for me; they are the same file. I will upload the schematic and layout asap. Thanks man..
Regards,
srivatsan

spice code:

* SPICE3 file created from stcm3.ext - technology: scmos

m1000 Vdd Gnd a_n57_n260 Vdd pfet w=1.8u l=43.2u
+ ad=271.08p pd=352.2u as=3.24p ps=7.2u
m1001 a_6_0 n13 nRb Vdd pfet w=172.8u l=1.8u
+ ad=194.4p pd=252u as=174.96p ps=226.8u
m1002 n21 n9 a_6_0 Vdd pfet w=43.2u l=1.8u
+ ad=38.88p pd=50.4u as=0p ps=0u
m1003 a_255_n22 a_255_n22 Vdd Vdd pfet w=28.2u l=0.6u
+ ad=50.76p pd=63.6u as=0p ps=0u
m1004 n178 n178 a_255_n22 Vdd pfet w=28.2u l=1.8u
+ ad=25.38p pd=31.8u as=0p ps=0u
m1005 Vdd n9 n9 Vdd pfet w=10.8u l=1.8u
+ ad=0p pd=0u as=19.44p ps=25.2u
m1006 a_60_n107 n13 Vdd Vdd pfet w=43.2u l=1.8u
+ ad=77.76p pd=100.8u as=0p ps=0u
m1007 n13 n9 a_60_n107 Vdd pfet w=43.2u l=1.8u
+ ad=38.88p pd=50.4u as=0p ps=0u
m1008 a_176_n107 n13 Vdd Vdd pfet w=43.2u l=1.8u
+ ad=77.76p pd=100.8u as=0p ps=0u
m1009 n7 n9 a_176_n107 Vdd pfet w=43.2u l=1.8u
+ ad=38.88p pd=50.4u as=0p ps=0u
m1010 n152 n13 Vdd Vdd pfet w=21.6u l=1.8u
+ ad=19.44p pd=25.2u as=0p ps=0u
m1011 a_n57_n260 n7 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=12.96p pd=54u as=121.5p ps=505.2u
m1012 n13 a_n57_n260 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=25.92p pd=108u as=0p ps=0u
m1013 n9 a_n57_n260 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=25.92p pd=108u as=0p ps=0u
m1014 Gnd n21 n178 Gnd nfet w=7.2u l=1.8u
+ ad=0p pd=0u as=12.96p ps=54u
m1015 a_64_n260 n21 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=25.92p pd=108u as=0p ps=0u
m1016 n21 n7 a_64_n260 Gnd nfet w=14.4u l=1.8u
+ ad=12.96p pd=54u as=0p ps=0u
m1017 a_112_n260 n21 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=25.92p pd=108u as=0p ps=0u
m1018 n13 n7 a_112_n260 Gnd nfet w=14.4u l=1.8u
+ ad=0p pd=0u as=0p ps=0u
m1019 a_160_n260 n21 Gnd Gnd nfet w=14.4u l=1.8u
+ ad=25.92p pd=108u as=0p ps=0u
m1020 n9 n7 a_160_n260 Gnd nfet w=14.4u l=1.8u
+ ad=0p pd=0u as=0p ps=0u
m1021 n7 n7 Gnd Gnd nfet w=3.6u l=1.8u
+ ad=6.48p pd=27.6u as=0p ps=0u
m1022 a_247_n230 a_247_n230 Gnd Gnd nfet w=9.3u l=0.6u
+ ad=16.74p pd=70.2u as=0p ps=0u
m1023 n152 n152 a_247_n230 Gnd nfet w=9.3u l=1.8u
+ ad=16.74p pd=70.2u as=0p ps=0u
C0 Vdd n152 4.3fF
C1 Vdd n7 5.5fF
C2 Vdd a_176_n107 3.6fF
C3 Vdd a_60_n107 3.6fF
C4 Vdd a_n57_n260 2.7fF
C5 Vdd n178 15.5fF
C6 Vdd a_255_n22 3.6fF
C7 Vdd n21 15.8fF
C8 n13 a_6_0 3.9fF
C9 n13 nRb 5.5fF
C10 Vdd a_6_0 9.7fF
C11 Vdd nRb 11.2fF
C12 n13 n9 3.2fF
C13 Vdd n9 54.8fF
C14 Vdd Gnd 16.8fF
C15 Vdd n13 77.2fF
C16 n21 n7 3.1fF
C17 nRb a_6_0 3.1fF
C18 a_160_n260 Gnd 4.8fF
C19 a_112_n260 Gnd 4.8fF
C20 a_64_n260 Gnd 4.8fF
C21 a_247_n230 Gnd 2.9fF
C22 n152 Gnd 11.0fF
C23 n7 Gnd 35.9fF
C24 a_176_n107 Gnd 9.2fF
C25 a_60_n107 Gnd 9.2fF
C26 a_n57_n260 Gnd 13.8fF
C27 n178 Gnd 17.9fF
C28 a_255_n22 Gnd 6.0fF
C29 n21 Gnd 30.9fF
C30 a_6_0 Gnd 23.2fF
C31 nRb Gnd 22.0fF
C32 n9 Gnd 20.7fF
C33 Gnd Gnd 190.2fF
C34 n13 Gnd 27.0fF
C35 Vdd Gnd 536.3fF

*Model for NMOS Transistor

.MODEL nfet NMOS ( LEVEL = 8
+VERSION = 3.2 TNOM = 27 TOX = 1.42E-8
+NCH = 1.7E17 VTH0 = 0.6106006
+K1 = 0.8791418 K2 = -0.0928691 K3 = 18.3613087
+K3B = -8.1787847 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 3.5655768 DVT1 = 0.3802648 DVT2 = -0.0874051
+U0 = 452.6968866 UA = 1.406301E-13 UB = 1.618501E-18
+UC = 5.36169E-12 VSAT = 1.802287E5 A0 = 0.5750334
+AGS = 0.1061895 B0 = 2.728576E-6 B1 = 5E-6
+KETA = -8.123787E-5 A1 = 4.190554E-4 A2 = 0.3323258
+RDSW = 1.06188E3 PRWG = 0.0883334 PRWB = 0.0315574
+WR = 1 WINT = 2.308608E-7 LINT = 7.347987E-8
+XL = 1E-7 DWG = -1.605516E-8
+DWB = 3.927415E-8 VOFF = 0 NFACTOR = 0.4571776
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.176689E-3 ETAB = -8.669487E-5
+DSUB = 0.0553447 PCLM = 2.4898877 PDIBLC1 = 1
+PDIBLC2 = 2.156583E-3 PDIBLCB = -0.0394428 DROUT = 0.9016259
+PSCBE1 = 6.238215E8 PSCBE2 = 1.760403E-4 PVAG = 0
+DELTA = 0.01 RSH = 83.8 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 1.97E-10 CGSO = 1.97E-10 CGBO = 1E-9
+CJ = 4.315315E-4 PB = 0.9194059 MJ = 0.4344423
+CJSW = 3.335714E-10 PBSW = 0.8 MJSW = 0.1985616
+CJSWG = 1.64E-10 PBSWG = 0.8 MJSWG = 0.1985616
+CF = 0 PVTH0 = 0.1570368 PRDSW = 187.3761409
+PK2 = -0.0254353 WKETA = -0.0181601 LKETA = 1.265053E-3 )
*



* Model for PMOS Transistor

.MODEL pfet PMOS ( LEVEL = 8
+VERSION = 3.2 TNOM = 27 TOX = 1.42E-8
+NCH = 1.7E17 VTH0 = -0.9836276
+K1 = 0.5265664 K2 = 0.0213923 K3 = 4.4911263
+K3B = -0.6532905 W0 = 1E-8 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.6487289 DVT1 = 0.4862165 DVT2 = -0.0896609
+U0 = 222.1424772 UA = 3.307877E-9 UB = 2.667897E-21
+UC = -5.80948E-11 VSAT = 2E5 A0 = 0.8813584
+AGS = 0.1156322 B0 = 7.044894E-7 B1 = 3.350124E-6
+KETA = 4.719307E-4 A1 = 0 A2 = 0.3
+RDSW = 3E3 PRWG = -0.0562354 PRWB = -5.560433E-3
+WR = 1 WINT = 2.962387E-7 LINT = 9.667582E-8
+XL = 1E-7 DWG = -3.741786E-8
+DWB = 1.377762E-8 VOFF = -0.0788978 NFACTOR = 0.6687895
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.4372057 ETAB = -0.0880016
+DSUB = 1 PCLM = 2.1801812 PDIBLC1 = 0.0430345
+PDIBLC2 = 3.544969E-3 PDIBLCB = -0.0720123 DROUT = 0.2036798
+PSCBE1 = 5.329158E9 PSCBE2 = 5E-10 PVAG = 0.2660196
+DELTA = 0.01 RSH = 106.9 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.72E-10 CGSO = 2.72E-10 CGBO = 1E-9
+CJ = 7.257637E-4 PB = 0.9604987 MJ = 0.4949935
+CJSW = 3.242689E-10 PBSW = 0.99 MJSW = 0.3345497
+CJSWG = 6.4E-11 PBSWG = 0.99 MJSWG = 0.3345497
+CF = 0 PVTH0 = 5.98016E-3 PRDSW = 14.8598424
+PK2 = 3.73981E-3 WKETA = 3.808346E-3 LKETA = -6.010447E-3 )
*


* MEASUREMENT OF CURRENTS THROUGH EACH BRANCH OF THE CIRCUIT


* Basic Biasing voltages
VD Vdd 0 DC 5
VG Gnd 0 DC 0
RB nRb Vdd 3.5k

* EXECUTION PART FOLLOWS..........
.tran 2e-6 2e-3

Added after 14 minutes:

Dear Vamsi:
Here is the schematic; the resistor has been changed to 3.5k for understanding the cirucit with respect to resistor variations. Hopefully they help you understand the cirucit... Thanks for the help..
Regards,
srivatsan

Added after 32 seconds:

Dear Vamsi:
Here is the schematic; the resistor has been changed to 3.5k for understanding the cirucit with respect to resistor variations. Hopefully they help you understand the cirucit... Thanks for the help..
Regards,
srivatsan

p.s.;: accidently did not attach the cirucit in the previous one.

 

[Vamsi Mocherla]

Dear Vatsan,

This is a constant transconductance circuit. The start up seems fine from the schematic. But I have two questions:

1. The ratios of the W/Ls of the transistors which are in the loop. I mean the PMOS transistors need to have different W/Ls for it to satisfy the equation VGS1 = VGS2 + IR. I hope that you have taken care of this thing.

2. The start up circuit needs a weak pull up transistor in PMOS. I see that the transitor is pretty strong. Kindly come back on this as well.

Added after 1 minutes:

My bad......Actually it is a weak pull up device. I got confused with the W and L. But can you reduce the length a little bit?

 

[srivatsan]

Dear Vamsi:
Since the Cadence was set up here just a year ago and they did not do a good job. Infact, I had to get the Spectre, CdsSpice and NGSpice installed and to get them running. Now the question is: Whether they run "correctly"? Well I think I am confident on NGSpice. Not on others, I really dont have a good reason ; a hunch.

Now to your questions:

1. You are right that W/L for the PMOS near the resistor is not "right".

I forgot to write the m=4 for that specific transistor (in schematic but is there in layout). Infact if you look at the spice code (from the layout), it is evident that there is one PMOS which is 4x of 43.2um. So It should be okay...

2. thats Okay... I did that to myself many times.. Hence I have an agreement that I never re-work on my own circuit after I am 100% sure the previous day.

Now; Few more questions to you:
1: Is it giving 40uA?
2: Since my L=1.8um, I see no reason to put dummy poly on either sides (Effect of RIE). Is this a good idea or not?

Please reply back. thanks.
regards,
Srivats