Need VHDL to Verilog translation,please! Thanks!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( enable1: in std_logic;
clk: in bit;
reset, reset1: in bit;
bcd_d: out std_logic_vector(7 downto 0));

end counter;

architecture arch of counter is
signal qint, qint1: std_logic_vector(3 downto 0);
signal full1: std_logic;
begin

CNT1 : process (enable1, clk, reset)

-- declarations

begin
if reset = '1' then
qint <= (others => '0');
elsif clk='1' and clk'event then
if enable1 = '1' then
if qint(0) = '1' and qint(3) = '1' then

full1 <= '1';

qint <= (others => '0');

else
qint <= qint + 1;
full1 <= '0';
end if;
end if;
end if;
bcd_d(3 downto 0) <= qint;
end process;

CNT2: process (full1, clk, reset1)
begin
if reset1 = '1' then
qint1 <= (others => '0');
elsif clk='1' and clk'event then
if full1 = '1' then
if qint1(0) = '1' and qint1(3) = '1' then
qint1 <= (others => '0');

else
qint1 <= qint1 + 1;

end if;
end if;
end if;
bcd_d(7 downto 4) <= qint1;
end process;
end arch;

This is a simple code and easy to code it in verilog. what actually you want to do after conversion? If you want to learn verilog then this is not the way.

There are some free VHDL to Verilog conversion tools available to convert simple or complex codes. please do a google search you will find them.

regards..