need to fix hold violation

[chanducs24]

hi

i had a one hold violation for one path, slack is -0.0027 after routing..can anyone guide me how to fix this and without any geometry violations after routing has been done?

Thanks,
chandra.

 

[jpvSoccer]

Hi,

How much more metal do you need to delay the signal enough to get rid of the violation?

Could you reroute the signal so that is travels a longer path?

 

[GI]

Hi Chandra,

There may be different approaches to fix it;
1 - If you don't want to modify any routing:

- a. Replace any of the cells on the timing path with their slower "pin compatible" versions. In your case the hold violation is very small, and I guess changing 1 cell should be sufficient.

- b. Replace the flop with a different hold time requirement. However this may be a little risky as it may also affect clock tree.

2 - If you are allowed to do ECO routing then add a buffer/delay cell to the violating pin. Then do ECO routing.

3 - You can also play with the routing to increase delay added by the routing itself. e.g. increasing the net length will increase the delay.

I hope it helps,
BR,
Gokhan
---

 

[chanducs24]

Thanks Gokhan..

ur information is helpful..

chandra.

 

[kumar_eee]

What is the setup margin available for the hold violating path?

If the setup margin is greater than +5 ps, then I would replace the driver cell of the D-Pin with "HVT" cell.

If the setup margin is just met, then I would choose any of the methods mentioned by Gokhan.

Hope this helps!.

 

[rca]

When I see a violation of 2.7ps, my first questions are :
1- clock and data deraiting?
2- hold time margin?
3- SI mode active?

If you have the SI mode enable, a marge around 100ps, and a debare of 5%, for me the design is "clean".