I am designing the LDO for a SoC application. therefore, the otuput cap is about 5 nF. No external cap, no ESR ...
I have no idea how the LHP zero comes into place...
Right now the problem is that, the 3rd pole and 4th pole are at low frequency and they are also very close to the UGB and the 2nd pole. I derived the position of the poles. But the 3rd and 4th poles are not where they are supposed to be.
I tried to tune the error amplifier. The 3rd and 4th poles donot move.......