need simple text lcd display VHDL code

[lupineye]

lcd vhdl

Hi! guru.
I'm challange to FPGA designer.

Can anyone write the simple VHDL code to display text on 16character 2line Text LCD for me?

I studied VHDL and recieved spartanII from my friend.

I want to implement and learn FPGA.

Thank you in advance.

 

[wiztronix]

vhdl code for lcd display

hahahaha! you are "CHALLENGING" VHDL programmers to do your homework for you?? is that what i see?? c'mon man.. that lcd thing is a piece of cake if ya know how FPGA works and how LCD works... its not really a good idea to get your stuff done on EDA... you'll learn nothing...

 

[lupineye]

vhdl lcd

Hi! wiztronix!

You may misunderstand me! I'm not a college student! I'm wireless and network engineer! I learned VHDL at school long time ago.
that would be easy for you. but not for me!

I intended to ask for helping. because I have a board and so excited. however, after I configurate on board. it didn't work.

there are many sources on the web.

Be humble! wiztronix!

 

[echo47]

lcd vhdl code

What type interface does your LCD have? There are many different kinds.

If the LCD is on a pre-built FPGA development board, what type board is it? The manufacturer probably has design examples that you can download.

 

[lupineye]

spartan 3e lcd vhdl

there are two boards. one has spartan2 chip(xc2s200) on it.
one is xc95108, maybe CPLD and 2 line text LCD, 4segments, 16 LED, VGA, and PS2 port. when my friend gave me that board. he didn't explain it in detail.

 

[echo47]

lcd display vhdl

That could be a fun board. Do you see any clues who manufactured it? They probably have schematics and application notes to make your life easier. If no luck, can you show us a photograph? Someone here may recognize it.

If still no luck, what's the part number on the LCD? Then we can find a data sheet and maybe example HDL code from someplace like https://www.fpga4fun.com or https://www.opencores.org/.

 

[lupineye]

vhdl lcd display

Hi!

I found the identity of this board!
It's manufactured by Digilent.

the board has LCD is called "Dio2". this board connected to the other board that has spartan2.

Please suggest me whether I buy new board or not
like spartan3 or vertexII pro..
As I heard, these boards has much better features than spartan2

 

[echo47]

vhdl code for lcd

You are in luck! Here's the documentation. You want to download everything for the D2 and DIO2, especially the two reference manuals. They explain the board features, including talking to the LCD. I also see ZIP files containing example ISE projects. I'll bet one of them contains sample LCD code.
**broken link removed**

Sure, the Spartan-II is an older generation FPGA, but you can still learn and have fun. You use the same development tools for all Xilinx FPGAs (except the really old ones).

If you want to try a modern FPGA, consider the inexpensive Spartan-3E starter kit from Xilinx. The board is actually made by Digilent. The kit includes the board, software, cables, and manuals.
**broken link removed**

Lots of companies make FPGA development boards containing a wide variety of I/O goodies and other features. Here's a pretty good list:
http://www.fpga-faq.org/FPGA_Boards.shtml

The Virtex-II Pro is getting old too. The Virtex-4 and brand new Virtex-5 FPGAs are very nice, but relatively expensive. The Spartan-3 and the newer Spartan-3E are good low-cost choices.

Is your DIO2 board sitting on that dime?

 

[lupineye]

spartan 3e lcd display

thank you! echo47!

I really appreciate your kindness!

 

[alimassster]

display vhdl

Give it a try .
https://www.fpga4fun.com
it may be helpful
good luck

 

[Black Jack]

lcd display program in vhdl

Hi!
See **broken link removed**

good luck

 

[manish12]

vhdl code lcd

Thank you to all for giveing so much information and links about LCD interface with FPGA.
I am trying it for my fun project which is use 16x2 lcd .

 

[yousuf14]

spartan 3 lcd vhdl

I need help too with spartan 3 started board. Problem is I want to use a VHDL block not a picoblaze. I can do wat ever with a pico blaze but not with VHDL.

 

[echo47]

spartan 3e lcd

Hi yousuf14,

What problem are you having with VHDL? If you are trying to learn Xilinx Project Navigator, try this procedure:
#754738

I'm not sure why you mentioned PicoBlaze if you don't want to use it.

 

[yousuf14]

vhdl code for lcd interfacing

Dear Echo47,
SOrry for my short message. I am a FPGA passinate FPGA desighner. I am trying to use the LCD display for the Spartan 3E Starter Board. I did not find any example or any material how to use it. I have the user guide and the example of the preloaded PicoBlack implementation of the Board.

I have made the following code which should work::

################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD is

port(
LCD_RSut std_logic;
LCD_RWut std_logic;
LCD_Eut std_logic;
clk:in std_logic;
SF_Dut std_logic_vector(3 downto 0)
);

end LCD;

architecture Behavioral of LCD is

signal substate,clock,clk1: integer:=0;
signal state: integer:=0;

begin

process(clk)
begin
clk1<=clk1+1;
if(clk1=0) then
clock<=clock+1;
--WAIT FOR 750000 CLOCK
if(state=0 and clock=750000) then
state<=1;
clock<=0;
--WRITE SF_D=0X3 FOR INIATION
elsif(state=1) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=2;
Clock<=0;
end if;
--WAIT FOR 2050000 CLOCK
elsif(state=2 and clock=205000) then
state<=3;
clock<=0;
--WRITE SF_D=0X3 FOR INIATION
elsif(state=3) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=4;
Clock<=0;
end if;
--WAIT 5000 CLOCK
elsif(state=4 and clock=5000) then
state<=5;
clock<=0;
--WRITE 0X3 FOR INITIATION
elsif(state=5) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=6;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=6 and clock=2000) then
state<=7;
clock<=0;
--WRITE SF_D=0X2 FOR INITIATION
elsif(state=7) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0010";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=8;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=8 and clock=2000) then
state<=9;
clock<=0;
--WRITE FUNCTION SET SD_F = 0X28
elsif(state=9) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0010";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="1000";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=10;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=10 and clock=2000) then
state<=11;
clock<=0;
--WRITE ENTRY SET SF_D = 0X06
elsif(state=11) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0110";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=12;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=12 and clock=2000) then
state<=13;
clock<=0;
--WRITE DISPLAY ON /OFF SD_F=0X0C
elsif(state=13) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="1011";
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=14;
Clock<=0;
end if;
--WAIT 2000 CLOCK
elsif(state=14 and clock=2000) then
state<=15;
clock<=0;
--WRITE CLEAR DISPLAY COMMAND SF_D<=0x HAVE TO FIX THIS
elsif(state=15) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="0000";-- I HAVE FIXED IT
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0001";-- I HAVE FIXED IT
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=16;
Clock<=0;
end if;
--WAIT FOR 82,000 CLOCK
elsif(state=16 and clock=82000) then
state<=17;
clock<=0;
--WRITE SET DD RAM ADD SF_D<=0x HAVE TO FIX THIS
elsif(state=17) then
if(substate=0 and clock=0) then
LCD_RS<='0';
LCD_RW<='0';
SF_D<="1000";--IT HAS BEEN FIXED
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0000";-- IT HAS BEEN FIXED
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=18;
Clock<=0;
end if;
--WAIT FOR 2,000 CLOCK
elsif(state=18 and clock=2000) then
state<=19;
clock<=0;
--WRITE DD RAM ADD SF_D<=0x HAVE TO FIX THIS
elsif(state=19) then
if(substate=0 and clock=0) then
LCD_RS<='1';
LCD_RW<='0';
SF_D<="0100";--IT HAS BEEN FIXED
Clock<=0;
substate<=1;
elsif(substate=1 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=2;
elsif(substate=2 and clock=12) then
LCD_E<='0';
substate<=3;
Clock<=0;
elsif(substate=3 and clock=48) then
SF_D<="0001";-- IT HAS BEEN FIXED
Clock<=0;
substate<=4;
elsif(substate=4 and clock=2) then
LCD_E<='1';
Clock<=0;
substate<=5;
elsif(substate=5 and clock=12) then
LCD_E<='0';
substate<=0;
state<=20;
Clock<=0;
end if;
elsif(state=20)then
state<=20;
clock<=0;
end if;

elsif(clk1=1) then
clk1<=0;
end if;
end process;
end Behavioral;

############

But it does not work at all. Model SIm shows that the wave forms are alright.

Please let me know if there is any helpful material.

Yousuf

Added after 1 minutes:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD is

port(
				 LCD_RS:out std_logic;
				 LCD_RW:out std_logic;
				  LCD_E:out std_logic;
					 clk:in std_logic;
					SF_D:out std_logic_vector(3 downto 0)
    );

end LCD;

architecture Behavioral of LCD is

signal substate,clock,clk1: integer:=0;
signal state: integer:=0;

begin

process(clk)
begin
clk1<=clk1+1;	
if(clk1=0) then
	   clock<=clock+1;
		--WAIT FOR 750000 CLOCK
		if(state=0 and clock=750000) then 
				state<=1;
				clock<=0;
		--WRITE SF_D=0X3 FOR INIATION
		elsif(state=1) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0011";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=2;
					 Clock<=0;
			end if;
		--WAIT FOR 2050000 CLOCK
		elsif(state=2 and clock=205000) then 
				state<=3;
				clock<=0;
		--WRITE SF_D=0X3 FOR INIATION 
		elsif(state=3) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0011";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=4;
					 Clock<=0;
			end if;
		--WAIT 5000 CLOCK
		elsif(state=4 and clock=5000) then 
				state<=5;
				clock<=0;
		--WRITE 0X3 FOR INITIATION
		elsif(state=5) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0011";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=6;
					 Clock<=0;
			end if;
		--WAIT 2000 CLOCK
		elsif(state=6 and clock=2000) then 
				state<=7;
				clock<=0;
		--WRITE SF_D=0X2 FOR INITIATION		
		elsif(state=7) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0010";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=8;
					 Clock<=0;
			end if;
		--WAIT 2000 CLOCK
		elsif(state=8 and clock=2000) then 
				state<=9;
				clock<=0;
		--WRITE FUNCTION SET SD_F = 0X28
		elsif(state=9) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0010";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="1000";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=10;
					 Clock<=0;
			end if;
		--WAIT 2000 CLOCK
		elsif(state=10 and clock=2000) then 
				state<=11;
				clock<=0;
		--WRITE ENTRY SET SF_D = 0X06
		elsif(state=11) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='0';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0110";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=12;
					 Clock<=0;
			end if;
		--WAIT 2000 CLOCK
		elsif(state=12 and clock=2000) then 
				state<=13;
				clock<=0;
		--WRITE DISPLAY ON /OFF SD_F=0X0C
		elsif(state=13) then 
			if(substate=0 and clock=0) then
					 LCD_RS<='0';
					 LCD_RW<='0';
					 SF_D<="0000";
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="1011";
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=14;
					 Clock<=0;
			end if;
		--WAIT 2000 CLOCK
		elsif(state=14 and clock=2000) then 
				state<=15;
				clock<=0;
		--WRITE CLEAR DISPLAY COMMAND SF_D<=0x HAVE TO FIX THIS
		elsif(state=15) then 
		   if(substate=0 and clock=0) then
					 LCD_RS<='0';
					 LCD_RW<='0';
					 SF_D<="0000";-- I HAVE FIXED IT
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0001";-- I HAVE FIXED IT
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=16;
					 Clock<=0;
			end if;
      --WAIT FOR 82,000 CLOCK			
		elsif(state=16 and clock=82000) then 
				state<=17;
				clock<=0;
		--WRITE SET DD RAM ADD SF_D<=0x HAVE TO FIX THIS
		elsif(state=17) then 
		   if(substate=0 and clock=0) then
					 LCD_RS<='0';
					 LCD_RW<='0';
					 SF_D<="1000";--IT HAS BEEN FIXED
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0000";-- IT HAS BEEN FIXED
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=18;
					 Clock<=0;
			end if;
      --WAIT FOR 2,000 CLOCK			
		elsif(state=18 and clock=2000) then 
				state<=19;
				clock<=0;
		--WRITE DD RAM ADD SF_D<=0x HAVE TO FIX THIS
		elsif(state=19) then 
		   if(substate=0 and clock=0) then
					 LCD_RS<='1';
					 LCD_RW<='0';
					 SF_D<="0100";--IT HAS BEEN FIXED
					 Clock<=0;
					 substate<=1;
			elsif(substate=1 and clock=2) then
					 LCD_E<='1';
					 Clock<=0;
					 substate<=2;
			elsif(substate=2 and clock=12) then
					 LCD_E<='0';
					 substate<=3;
					 Clock<=0;
			elsif(substate=3 and clock=48) then 
					 SF_D<="0001";-- IT HAS BEEN FIXED
					 Clock<=0;
					 substate<=4;
			elsif(substate=4 and clock=2) then
					 LCD_E<='1';	
					 Clock<=0;
					 substate<=5;
			elsif(substate=5 and clock=12) then
					 LCD_E<='0';
					 substate<=0;
					 state<=20;
					 Clock<=0;
			end if;
		elsif(state=20)then
			  state<=20;
			  clock<=0;
		end if;

elsif(clk1=1) then
	clk1<=0;
end if;
end process;
end Behavioral;

 

[echo47]

spartan 3e lcd code

Hi yousuf14,
I don't speak VHDL very well. Hopefully someone else can help you debug your code.
What is your code suppose to do, and what does it actually do?
Your code doesn't have any pin number assignments. Are they in your UCF?

Please edit your previous message and delete the long duplicate code section.

Maybe this Verilog example will help you. It works on my Xilinx Spartan-3E Starter Kit.
It repeatedly clears the display and prints "Hello World!".
The LCD timing is crude, not optimized. I slowed it down so I can see the individual character updates.

module top (clk, sf_ce0, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
                    parameter       k = 18;
  (* LOC="C9" *)    input           clk;        // synthesis attribute PERIOD clk "50 MHz"
                    reg   [k+8-1:0] count=0;
  (* LOC="D16" *)   output reg      sf_ce0;     // high for full LCD access
                    reg             lcd_busy=1;
                    reg             lcd_stb;
                    reg       [5:0] lcd_code;
                    reg       [6:0] lcd_stuff;
  (* LOC="L18" *)   output reg      lcd_rs;
  (* LOC="L17" *)   output reg      lcd_rw;
  (* LOC="M15" *)   output reg      lcd_7;
  (* LOC="P17" *)   output reg      lcd_6;
  (* LOC="R16" *)   output reg      lcd_5;
  (* LOC="R15" *)   output reg      lcd_4;
  (* LOC="M18" *)   output reg      lcd_e;

  always @ (posedge clk) begin
    count  <= count + 1;
    sf_ce0 <= 1;
    case (count[k+7:k+2])
       0: lcd_code <= 6'h03;        // power-on initialization
       1: lcd_code <= 6'h03;
       2: lcd_code <= 6'h03;
       3: lcd_code <= 6'h02;
       4: lcd_code <= 6'h02;        // function set
       5: lcd_code <= 6'h08;
       6: lcd_code <= 6'h00;        // entry mode set
       7: lcd_code <= 6'h06;
       8: lcd_code <= 6'h00;        // display on/off control
       9: lcd_code <= 6'h0C;
      10: lcd_code <= 6'h00;        // display clear
      11: lcd_code <= 6'h01;
      12: lcd_code <= 6'h24;        // H
      13: lcd_code <= 6'h28;
      14: lcd_code <= 6'h26;        // e
      15: lcd_code <= 6'h25;
      16: lcd_code <= 6'h26;        // l
      17: lcd_code <= 6'h2C;
      18: lcd_code <= 6'h26;        // l
      19: lcd_code <= 6'h2C;
      20: lcd_code <= 6'h26;        // o
      21: lcd_code <= 6'h2F;
      22: lcd_code <= 6'h22;        //
      23: lcd_code <= 6'h20;
      24: lcd_code <= 6'h25;        // W
      25: lcd_code <= 6'h27;
      26: lcd_code <= 6'h26;        // o
      27: lcd_code <= 6'h2F;
      28: lcd_code <= 6'h27;        // r
      29: lcd_code <= 6'h22;
      30: lcd_code <= 6'h26;        // l
      31: lcd_code <= 6'h2C;
      32: lcd_code <= 6'h26;        // d
      33: lcd_code <= 6'h24;
      34: lcd_code <= 6'h22;        // !
      35: lcd_code <= 6'h21;
      default: lcd_code <= 6'h10;
    endcase
  //if (lcd_rw)                     // comment-out for repeating display
  //  lcd_busy <= 0;                // comment-out for repeating display
    lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;  // clkrate / 2^(k+2)
    lcd_stuff <= {lcd_stb,lcd_code};
    {lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
  end
endmodule

 

[yousuf14]

lcd interfacing vhdl code

Thank You soo much for the veryog code.

My code actually puts an A in the LCD display. Well that is actually what it suppose to do. But it is not working. Yes I am using UCF.

I followed the user guied timing. I think your way is much better as it insure everything. I dont thing we need a complex code that will me 100% accurate. That is why I am using your methode to do my stuff.

 

[lamekan]

vhdl lcd code

dear yousuf14;
i solved your problem with vhdl code for lcd that you write.

as i understand u used 50mhz internal clock as clk input but u didnot actually used it in your code it appears only top of the code. clk1 is not neccesary.
i think you must erase clk1 and add this after process begins:

if clk'event and clk='1' then.....

however the other but more important mistake that u did is making the display on/of "1001".. it says that display is off. thir bit of this must be 1 to see anything on lcd. for example yu could do it as 1100 or 1111 or 1101 or 1110. last two digits determines the existence of the cusor and either it blinks or not...


if i could help u i wil be happy

Added after 2 minutes:

i tested your code after making corrections above and it worked succesfully

Added after 1 minutes:

i should also say that your code is inefficient to write more than 4 characters on lcd. its synthesise job takes more than 3 hours...

you should find any way to increase your code reliability...

see ya

 

[ananthu]

display lcd vhdl

hello friends,

i need FPGA-GLCD interfacing Verilog code. FPGA is Spartan-III version whereas GLCD is 128×64 display type and is based on KS0108 LCD controller (JHD12864E). Please do help me at least with what all things I need to do, if you know that.

ananthu

 

[clarken]

vhdl display

Hi,
I wrote the code for initialization and clear the display only . But when running , the LCD is not cleared . Can any expert check the code for me .. I check a lot of time but can not find any error. When doing simulation , i think it can not move to the state 8 ..thank in advance
----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD_Display is
port(clk,reset,start : in std_logic;
-- data_in : in std_logic_vector(7 downto 0);
stop: out std_logic;
ready : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_E : out std_logic;
SF_D : out std_logic_vector(3 downto 0)
);
end entity LCD_Display;

architecture behavior of LCD_Display is
type state_type is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9,stop_state);
signal state_reg, state_next : state_type;
signal count, count_reg: integer;
signal decision,decision_reg : integer;
signal finish : std_logic;
signal initial : std_logic;
--signal stop : std_logic;
signal data : std_logic_vector(9 downto 0);

begin
process(clk,reset) is
begin
if reset = '1' then
state_reg <= state0;
count_reg <= 0;
decision_reg <= 0;
elsif clk' event and clk = '1' then
state_reg <= state_next;
count_reg <= count;
decision_reg <= decision;
end if;
end process;

process(start,count_reg,state_reg)
variable wait1,wait2,wait3,wait4,wait5 : integer;
begin
---
--state_next <= state_reg;
count <= count_reg;
ready <= '0';
decision <= decision_reg;
case state_reg is
when stop_state =>
stop <= '1';

when state0 =>
initial <= '1';
count <= 0;
wait1 := 750000; ---- in power initalization , 1st 750k , 205k,5k,2k time clock 50 Mhz
wait2 := 205000;
wait3 := 5000;
wait4 := 2000;
if start = '1' then
finish <= '0';
state_next <= state1;
-- wait5 := 840000; ----- time for clear display
decision <= 0 ; ---- signal indicate where to go
else
state_next <= state0; ---- not start yet
end if ;
---%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%-----------------------------------
---%%%%%%%%%%% State 1 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%-----------------------------------------------
when state1 => --- this state to determine to finish initilization and start write expected data
count <= count_reg + 1;
if decision = 0 then ---- wait 750k first
if count > wait1 then ---- start to count until read 750k
count <= 0; --- reassign count = 0
data <= "1000000011"; --- data signal for assign LCD_RS, RW and SW_F
decision <= 1; --- after finish, move to the 2nd wait 205k
state_next <= state2; --- move to state2 for assign SW_F as initialzaiotn required
else
state_next <= state1;
end if;

elsif decision = 1 then
if count > wait2 then ---- start to count until reach 205k
count <= 0; --- reassign count = 0
data <= "1000000011"; --- data signal for assign LCD_RS, RW and SW_F = 0X3
decision <= 2; --- after finish the write SW_F, move to the 3rd wait 5k
state_next <= state2; --- move to state2 for assign SW_F as initialzaiotn required
else
state_next <= state1;
end if;

elsif decision = 2 then
if count > wait3 then ---- start to count until reach 5k
count <= 0; --- reassign count = 0
data <= "1000000011"; --- data signal for assign LCD_RS, RW and SW_F = 0X3
decision <= 3; --- after finish the write SW_F, move to the 3rd wait 5k
state_next <= state2; --- move to state2 for assign SW_F as initialzaiotn required
else
state_next <= state1;
end if;

elsif decision = 3 then
if count > wait4 then ---- start to count until reach 2k
count <= 0; --- reassign count = 0
data <= "1000000010"; --- data signal for assign LCD_RS, RW and SW_F = 0X2
decision <= 4; --- after finish the write SW_F, move to the 3rd wait 5k
state_next <= state2; --- move to state2 for assign SW_F as initialzaiotn required
else
state_next <= state1;
end if;

elsif decision = 4 then --- issue Function set
if count > wait4 then
count <= 0;
data <= "0000101000";
decision <= 5;
state_next <= state2;
else
state_next <= state1;
end if;

elsif decision = 5 then -- entry mode set
if count > wait4 then
count <= 0;
data <= "0000000110";
decision <= 6;
state_next <= state2;
else
state_next <= state1;
end if;

elsif decision = 6 then --- display on off
if count > wait4 then
count <= 0;
data <= "0000001100";
decision <= 7;
state_next <= state2;
else
state_next <= state1;
end if;

else--if decision = 7 then --clear display
if count > wait4 then
count <= 0;
data <= "0000000001";
decision <= 8;
finish <= '1';
state_next <= state2;
else
state_next <= state1;
end if;
-- else --- decision = 8
-- state_next <= stop_state;
end if;
-- else
-- if count > wait4 then
-- count <= 0 ;
-- data <= "10" & "01000001" ;
-- ready <= '0';
-- state_next <= state2;
-- else
-- state_next <= state1;
-- end if;
--
-- end if ; --- end state1

--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%----
--%%%%%%%% State 2: assign value for LED_RS, RW and SW_F%---------
when state2 =>
LCD_RS <= data(9);
LCD_RW <= data(8);
SF_D <= data(7 downto 4);
state_next <= state3;
initial <= '0';
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%----
--%%%%%%%% State 3-> 8: write SW_F for display%---------
when state3 =>
count <= count_reg + 1 ;
if count > 2 then
count <= 0;
LCD_E <= '1';
state_next <= state4;
else
LCD_E <='0';
state_next <= state3;
end if;

when state4 =>
count <= count_reg + 1;
if count > 12 then
count <= 0;
LCD_E <= '0';
state_next <= state5;
else
state_next <= state4;
LCD_E <= '1';
end if;

when state5 =>
count <= count_reg + 1;
if count > 48 then
count <= 0;
SF_D <= data(3 downto 0);
LCD_RS <= data(9);
LCD_RW <= data(8);
state_next <= state6;
else
state_next <= state5;
end if;

when state6 =>
count <= count_reg + 1;
if count > 2 then
count <= 0;
LCD_E <= '1';
state_next <= state7;
else
state_next <= state6;
LCD_E <= '0';
end if;

when state7 =>
count <= count_reg + 1;
if count > 12 then
count <= 0 ;
LCD_E <= '0';
state_next <= state8;
else
state_next <= state7;
LCD_E <= '1';
end if ;

when state8 =>

--if finish = '1' then
if decision = 8 then
state_next <= state9;
else
state_next <= state1;
end if;

when state9 =>
count<= count_reg +1;
if count > 82000 then
count <= 0;
state_next <= stop_state;
else
state_next <= state9;
end if;
end case;
end process;
end architecture behavior;
----------------------------------------------------------------------------------------