Need LDO expert's help

Hi :
For stability ,it is required that the output cap must be greater than a value ,but
the ESR is not needed . So is it output cap compensation and the output pole is
the dominant pole ? But in it's shcmatic , it is like that a node in the errorAmp
is made the dominant pole for there is Miller compensation with cap Multiplier .
So what kind of compensation and which pole is the dominant pole ?

of course the dominant pole is at the output. ESR is also important for stalibity.

usually u use a large offchip cap. at the output node making the output node the dominant pole , or if u don't want offchip component u use other compansation techniques (like miller , nested miller or whatever)to make the output of the error amp. the dominant pole

usually u use a large offchip cap. at the output node making the output node the dominant pole , or if u don't want offchip component u use other compansation techniques (like miller , nested miller or whatever)to make the output of the error amp. the dominant pole
------ NONSENSE

I think usually we creat a zero in the circuit to compensate the output pole, the dominate pole usually is inside.

I don't think so, the dominate pole usually is the output pole,and creat a zero to compensate the output pole of errorAmp. because the LDO's output pole and CAP's esr-res is variable

Agree with paley.

Traditional LDO design, domainant pole 99.99999% result from output cap(Co). in real life design, this is a real capicator, therefore, it is not an ideal cap and will have resistance, it is know as Resr. Because of Resr, there is a zero.

Co master the domainant pole, the zero will cancel the 2nd pole from AMP's output. There is also, a high frequency pole, that is behind UGF.(*but i forgot where it is from, and i am lazy to check this out to u now*)

So, it may be or most liekly that, there is 3 pole, 1 zero in typical LDO.

People nowadays plays LDO at least in the following ways :

1> due feedback loop.
2> break down final stage into smaller piece on PMOS in order to create more pole/zero pairs by feebback control.
3> damping effect control.
4> adding zero in some place btween domainant pole and UGF


all these methods are........playing with maths and then turn it into circuit...

All are the things i know upon now. In fact, if u have time to study LDO papers. u should discover how people playing on LDO. and u must got more more knowledge on circuit design ~


i hope u will draw the same conclusion as me so that there is one more ppl prove i am right or....there is two ppl wrong in the world.....................

u can refer to the ieee paper "a_capacitor-free_cmos_low-dropout_regulator".
It gives u a general image about the conventional ldo,and proposes a damping method to stabilize the ldo.
Hope it will help~~