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It depends on the phase detector type and it's capabilities and also on your definition of locked state. To my opinion there's no exact definition. You may e.g. consider the single occurence of a phase difference between reference and VCO above a certain limit as out-of lock condition. This implies a means to measure phase differences.
Generally, the application specific requirements of PLL performance are setting the locked criterion.
Some chips have a lock detector pin on them already, others you have to design one yourself.
For the standard discrete phase frequency detector chip, you get pulses of random frequency out of the phase detector when it is not locked. You AC couple that to a shottky diode, and store the charge generated across a capacitor. Once the voltage across the capacitor rises beyond a threshold point, you sense that with a comparator that reports the out-of-lock condition.
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