I’m trying to design, in Cadence, a single-ended CMOS AMPOP in technology 0,35 µm with a Bandwidth of 100MHZ. I'm thinking to design a simple OTA but I haven't decided yet.
I would like to ask if someone can give me or advice me some kind of information/book to help me:?:
i advice u first stage folded cascode (PMOS as input) and second stage is CS (sure NMOS the input), this circuit gives u low in settling time and high gain with phase margin
regards
i advice u first stage folded cascode (PMOS as input) and second stage is CS (sure NMOS the input), this circuit gives u low in settling time and high gain with phase margin
regards
CS maybe is common source amp.
But the Bandwidth of 100MHZ is too large. Is it the unit gain bandwidth, but not the -3dB bandwidth.
I think it is hard to design an OTA with 100MHZ -3dB bandwidth. It will need a very large bias current to get a large gm.
CS maybe is common source amp.
But the Bandwidth of 100MHZ is too large. Is it the unit gain bandwidth, but not the -3dB bandwidth.
I think it is hard to design an OTA with 100MHZ -3dB bandwidth. It will need a very large bias current to get a large gm.