module car_window(clk,clr,data_up,data_down,move_up,move_down,auto_move_up,auto_move_down,stop_move);
//IO ports
input clk,clr,data_up,data_down,stop_move;
output move_up,move_down,auto_move_up,auto_move_down;
wire clk,clr,data_up,data_down,stop_move;
reg [7:0] counts;
reg move_up,move_down,auto_move_up,auto_move_down,break;
initial
begin
break = 1'b0;
counts = 8'b0;
move_up = 1'b0;
move_down = 1'b0;
auto_move_up = 1'b0;
auto_move_down = 1'b0;
end
always @(posedge data_up or posedge data_down)
begin
break=1'b1;
end
always @(posedge clk)
begin
if (data_up==1'b0 | data_down==1'b0)
begin //5
counts=1'b0;
move_up=1'b0;
move_down=1'b0;
end //5
end
always @(posedge clk)
begin
if (stop_move==1'b1 | break==1'b1)
begin
if (move_up==1'b1) move_up=1'b0;
if (move_down==1'b1) move_down=1'b0;
if (auto_move_up==1'b1) auto_move_up=1'b0;
if (auto_move_down==1'b1) auto_move_down=1'b0;
if (break==1'b1) break=1'b0;
end
end
always @(posedge clk)
begin //1
if (data_up==1'b1)
begin //3
counts = counts + 8'b01;
if (counts === 8'b111) auto_move_up = 1'b1;
if (move_up==1'b0) move_up=1'b1;
end //3
else if (data_down==1'b1)
begin//4
counts = counts + 8'b01;
if (counts === 8'b111) auto_move_down = 1'b1;
if (move_down==1'b0) move_down=1'b1;
end//4
end //1
endmodule
im new in HDL-verilog!Can someone help!
i simulate with modelsim and everything is ok!but when i try to synthesize with Leonardo i get the following error
"C:/VERILOG/Examples/Car_windows.v", line 24: Error, More than one untested edge trigger; cannot infer clock for this always statement
Error(s) found in Verilog source."