ithought about it but it didn't help. i tried to compile it now:
Code Verilog - [expand] |
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| module fib(number, value);
input number;
output value;
wire number;
reg value;
reg v1;
reg v2;
if(number < 2)
assign value = number;
else
begin
fib f1 (number-1,v1);
fib f2 (number-2,v2);
assign value = (v1+v2);
end
endmodule |
and got the errore:
# ** Error: I:/project/fib/fib.v(11): The generate if condition must be a constant expression.
# ** Error: I:/project/fib/fib.v(12): Register is illegal in left-hand side of continuous assignment
# ** Error: I:/project/fib/fib.v(17): Register is illegal in left-hand side of continuous assignment