hoangthanhtung
Full Member level 3
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Simulation with Verilog
I have a module based on Verilog. I also have input/output data files in term text file. Theyt contain signed integers and is generated by Matlab.
I want to Simulation my module by using ModelSim like as
- Read input file correspond with clock signal as a testbench signal
- Simulation by using my module
- Write output of my module to other file (in term of text file)
Is there anybody who can help me ! If you have any example that mention in my problem, could you send to my by email
httung@asic.korea.ac.kr
Thank in advance
I have a module based on Verilog. I also have input/output data files in term text file. Theyt contain signed integers and is generated by Matlab.
I want to Simulation my module by using ModelSim like as
- Read input file correspond with clock signal as a testbench signal
- Simulation by using my module
- Write output of my module to other file (in term of text file)
Is there anybody who can help me ! If you have any example that mention in my problem, could you send to my by email
httung@asic.korea.ac.kr
Thank in advance