[SOLVED] Need help with design of cs stage amplifier with pmos current source load

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Basu_Gouda

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Hi


I am having problem in designing the amplifier as the output is lagging than the input provided. Here are the few snapshot of the design.

Is the design correct.

 
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Hi

Thanks for the reply though I am unable to get the correct output and there is no phase shift at the input. Providing Vb as 2.5v DC and the Vin is analog signal
 

A large amount of gate capacitance could conceivably alter the phase.

I do not know of a way to experiment with gate capacitance in simulation, so I couldn't say how much it would need to be, in order to produce the amount of current leading in your scope trace.
 

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