Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Need help with buffer design which input varies from 0 - Vdd

Status
Not open for further replies.
Sadegh.j

Sadegh.j

Advanced Member level 3
Advanced Member level 3
Joined
Nov 29, 2006
Messages
749
Helped
48
Reputation
98
Reaction score
15
Trophy points
1,298
Activity points
5,585
Buffer design

Hi

I am trying to design a buffer whose input varies from 0 to Vdd, (almost from zero to almost Vdd) and has a minimum level shift. Any suggestions? The frequency is about 5 Ghz in 0.13um CMOS technology.

Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top