rg350dxlover
Member level 1
Hi... I'm new to VHDL and I have to do the code for 8 to 3 encoder. There seem to be a problem with my code but I can't figure out what it is. Help! Thanks...
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port( y : in std_logic_vector(7 downto 0);
s : out std_logic_vector(2 downto 0));
end encoder;
architecture behavior of encoder is
begin
with y
s <= "000" when "0000 0001"
"001" when "0000 0010"
"010" when "0000 0100"
"011" when "0001 0000"
"100" when "0010 0000"
"101" when "0100 0000"
"110" when "1000 0000"
end behavior;
library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port( y : in std_logic_vector(7 downto 0);
s : out std_logic_vector(2 downto 0));
end encoder;
architecture behavior of encoder is
begin
with y
s <= "000" when "0000 0001"
"001" when "0000 0010"
"010" when "0000 0100"
"011" when "0001 0000"
"100" when "0010 0000"
"101" when "0100 0000"
"110" when "1000 0000"
end behavior;