Need help to simulate verilog code in modelsim 6.2c

[vinod.ailsinghani]

Hi friends,
I have just enrolled to this community.
i am using two EDA tools like Modelsim SE 6.2c and Xilinx 13.2 for verilog RTL coding.
I m getting weird problem in modelsim SE PLUS 6.2c while simulating verilog (i.e. adding signal to wave) code like '# (vish-4014) No objects found matching'? .moreover i also noticed that my main code and test bench are not bounded (unlike in vhdl) whereas same code works or simulated properly on xilinx ISE 13.2 tool? why this is? i am new to verilog language?
however,how to make use of modelsim SE plus 6.2 tool for system verilog (i mean what sort of setting i need to do in tools)?please help me out

main code is :
module Latches (J,K,D,En,reset,Qd,Qd_Bar,Qjk,Qjk_Bar);
input J,K,D,En,reset;
output Qd,Qd_Bar,Qjk,Qjk_Bar;
reg Qd,Qd_Bar,Qjk,Qjk_Bar;

always @(En or reset or D)
begin
if (reset == 1)
begin
Qd <= 0;
Qd_Bar <= 1'b1;
end
else if (En == 1)
begin
Qd <= D;
Qd_Bar <= ~(D);
end
end

always @ (En,reset,J,K) // verilog 2001 way of writing always block
begin
if (reset == 1)
begin
Qjk <= 1'b0;
Qjk_Bar <= 1'b1;
end
else if (En == 1)
begin
if (J == 1 && K == 0)
begin
Qjk <= 1'b1;
Qjk_Bar <= 1'b0;
end
else if (J == 0 && K == 1)
begin
Qjk <= 0;
Qjk_Bar <= 1'b1;
end
else if (J == 1 && K == 1)
begin
Qjk <= ~(Qjk);
Qjk_Bar <= ~(Qjk_Bar);
end
end
end
endmodule

and its test bench code is:
`timescale 1ns/1ns

module TB_Latches;
reg TB_J,TB_K,TB_D,TB_En,TB_reset;
wire TB_Qd,TB_Qd_Bar,TB_Qjk,TB_Qjk_Bar;
Latches uut (
.J(TB_J),
.K(TB_K),
.D(TB_D),
.En(TB_En),
.reset(TB_reset),
.Qd(TB_Qd),
.Qd_Bar(TB_Qd_Bar),
.Qjk(TB_Qjk),
.Qjk_Bar(TB_Qjk_Bar)
);

initial
fork
// initialize inputs
TB_J = 0;
TB_K = 0;
TB_D = 1'b0;
TB_En = 0;
TB_reset = 0;

// Add stimulus here
#5 TB_reset = 1;
#10 TB_reset = 1'b0;
#17 TB_D = 1'b1;
#20 TB_En = 1;
#25 TB_En = 0;
#20 TB_J = 1;
#5 TB_En = 1;
#10 TB_D = 0;
#20 TB_K = 1;
#10 TB_J = 0;
#10 TB_K = 0;
#15 TB_J = 1;
#14 TB_D = 1;
#40 TB_J = 0;
#10 TB_K = 0;
#10 TB_En = 0;
#65 TB_J = 1;
#14 TB_En = 1;
#75 TB_En = 0;
#120 TB_K = 1;

join
// end of intial design module
endmodule





regards,
Vinod