need help to create eight demuxs

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20vt

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I im new to vhdl and need some help
how to make eight demux 2 to 1 which share same Sel ?
I did one demux 2 to 1
entity demux is
port(d,s:in bit ;

z0,z1: out bit );
end demux ;

architecture arc_demux of demux is
begin
z0 <= d and (not s);
z1 <= (d and s);
end arc_demux ;

how I can make eight of it?
 

As you did it for a 2:1 you do it for a 8 bit demux.
Your input signals are d, s0, s1 and s2, while your output are z0 to z7. What remain is only to translate your truth table relating z(i) to inputs into a vhdl code.
 

Yes thank you but its not working ill more time
 

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