Need Help regarding Actel FPGA Area Constraints

[saad_sipra]

I am looking for help about adding area constraints for actel fpga . i am using Libero soc 11.5. how to access a perticular logic cell (resource) for a logic using Chip Planner or writing through constraint files.

 

[shaiko]

I'd try doing it through the synthesis tool under the hood of the Libero IDE - Synopsys Simplify.

But what is it exactly that you're trying to achieve?
I wouldn't expect major improvements in FPGA resource usage with this approach ...
The RTL itself is where I would look first.

 

[saad_sipra]

actually, i have written a firmware, synthesis was done rightly but every time after implementation it changes its behavior in hardware without changing anything in firmware. that was obvious, i find some timing slacks in the report ,which i need to cater but could not meet the minimum delay timings for clock signals in Timing analyzer. that is the basic problem, need your suggestions?

 

[ads-ee]

Well Microsemi's Libero has a really really really really bad placer...it's so bad that if you have a 8-bit bus the output registers going to the output pins (if you don't allow the tools to use the I/O registers) will place all the output registers in a clump and the clock to output pin delays will be all over the place. This happens even if you have extremely tight constraints (the first indication of a problem is you don't meet timing and then find out why 8-O)

- - - Updated - - -

actually, i have written a firmware, synthesis was done rightly but every time after implementation it changes its behavior in hardware without changing anything in firmware.

That's probably because Microsemi sill uses some crummy annealing algorithm that uses a random seed, i.e. like Xilinx/Altera did back in the 90's. ;-)

To fix you problems with timing, use placement constraints like you asked about. Unfortunately I don't remember the syntax for them, but found them in Microsemi's documentation originally, it wasn't hard to do, they had some examples of how to write the constraints.

 

[saad_sipra]

I have read some documentations about adding timing constraints using smart time and about adding area constraints using chip planner as well as as writing TCL commands.
1) to remove the time slack for a dedicated path i added minimum delay using smart time, but that didn't worked.
2) I reassigned the resources by placing the logic in new unused place in chip planner to adjust that particular delay , but unable to do so..

 

[shaiko]

When you say "that didn't work" - do you mean:

1. The command gets doesn't get applied successfully.
2. The command gets applied successfully but doesn't solve the timing issue.

?

 

[ThisIsNotSam]

I have read some documentations about adding timing constraints using smart time and about adding area constraints using chip planner as well as as writing TCL commands.
1) to remove the time slack for a dedicated path i added minimum delay using smart time, but that didn't worked.
2) I reassigned the resources by placing the logic in new unused place in chip planner to adjust that particular delay , but unable to do so..

I don't understand your goal here. What is the meaning of 'remove the time slack'? Time slack is a good thing, you want to keep it!

 

[ads-ee]

I don't understand your goal here. What is the meaning of 'remove the time slack'? Time slack is a good thing, you want to keep it!

Maybe they think having slack has to be fixed so it's always 0?

 

[ThisIsNotSam]

Maybe they think having slack has to be fixed so it's always 0?

That is what I am afraid of, yes.

 

[saad_sipra]

When you say "that didn't work" - do you mean:

1. The command gets doesn't get applied successfully.
2. The command gets applied successfully but doesn't solve the timing issue.

?

Dear Shaiko,
command gets applied successfully , but timing issues were not solved , then i just added 'False path constraints '. it resolved the issue as i checked maximum and minimum timings in smart time tool.

 

[saad_sipra]

That is what I am afraid of, yes.

Dear ,
Kindly guide me ,if i am wrong.....:thinker:
I think that having slacks ( - values) means timing constraints are not accurate and i had to add some delays or something to make it correct.

 

[ads-ee]

Dear Shaiko,
command gets applied successfully , but timing issues were not solved , then i just added 'False path constraints '. it resolved the issue as i checked maximum and minimum timings in smart time tool.

Uh, do you know why you used a false path constraint? Is it because the path is failing timing or because the path is not supposed to have any constraint on it's delay. If you can guarantee that by design it doesn't matter if the delay through that path is 0.00001 ns or 100000000 seconds then applying the false path to that path is probably okay.

Dear ,
Kindly guide me ,if i am wrong.....:thinker:
I think that having slacks ( - values) means timing constraints are not accurate and i had to add some delays or something to make it correct.

Negative slack is bad it means you are missing timing by that amount (you have to fix the problem). Positive slack on the other hand is good, it means you've passed timing with extra margin.

 

[ThisIsNotSam]

Please learn about false_paths, you might have just killed your design with an incorrect false_path constraint.

 

[shaiko]

Dear Shaiko,
command gets applied successfully , but timing issues were not solved , then i just added 'False path constraints '. it resolved the issue as i checked maximum and minimum timings in smart time tool.

You use the 'false path' constraint when the path in question has absolutely no value for timing analysis.
For example:

1. A signal that crosses between asynchronous time domains.
2. A signal that drives an LED.

In short - a path that you (as the designer) know cause setup/hold time violations and willingly able to accept that.

 

[vGoodtimes]

Incorrectly using false_path is worse than having a timing error. Normally, the tools would attempt to meet timing for a difficult path. With false_path applied, there is no intentional optimization for that path.

The second issue is that with/without false_path applied, a failing path may not always fail. This can lead to a belief that the design works and that the false_path was used correctly. The issue is that temperature/voltage changes could cause the design to fail in the future.

 

[incisive29]

I want to know how do you add "input delays" to the external clocks which are the cause of negative slack in the design?
What parameters should i consider for calculating input delays for my external clock to remove slack?

 

[ads-ee]

I want to know how do you add "input delays" to the external clocks which are the cause of negative slack in the design?

It is a very common issue, there are quite a few resources to learn how to write set_input_delay constraints in SDC.
http://ebook.pldworld.com/_Semiconductors/Actel/Libero_v70_fusion_webhelp/set_input_delay_(sdc_input_delay_constraint).htm
http://quartushelp.altera.com/15.0/mergedProjects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_set_input_delay.htm
http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

Just as a sample of the numerous links provided by a google search on "set_input_delay constraint example"

What parameters should i consider for calculating input delays for my external clock to remove slack?

Didn't you read the other posts? The term remove slack is exceptionally bad English and technically a horrible thing to do.

What you mean is "I want to fixed failing timing constraints", or "I want to fix my negative slack".

 

[incisive29]

This is precisely what I mean. I did mention negative slack earlier. Anyway, thnx for the links.

 

[ThisIsNotSam]

I want to know how do you add "input delays" to the external clocks which are the cause of negative slack in the design?
What parameters should i consider for calculating input delays for my external clock to remove slack?

This is not a sound approach unless you can guarantee an external clock is synchronous to another clock. Typically, input delays are used for data pins, not for clock pins.

 

[vGoodtimes]

Is the failing path on IO, or within the device? What is the clock rate, the timing constraint, and the amount of the negative slack?

Using input delay for the clock makes sense if there is a timing issue with an input to the FPGA.