Need help performing stability analysis on an op-amp being used in a current source

pr0wl3r

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Hi, I have to perform stability analysis on an op-amp (AD8671) which is being used as an op-amp in the circuit attached. I am using LTSpice to perform this. My approach is to give a 1V AC small signal at the input and see the frequency response at the 'testpoint' which should, if I am correct, provide me with the gain and phase of the transfer function. For this, I am trying to adjust the conditions so that I am able to create critical points, with (Gain > 1) and (Phase Shift = 180 degrees). I also need to check the effect of the snubber circuit attached to the node, as theoretically, with improper values of the same, the response should be unstable.

However, as of yet, I am unable to effectively see this, primarily because the gain is always <-160 dB as shown in attached image, in both open loop and closed loop conditions. Also, if I try to perform a transient analysis, the simulation is jittery, often getting stuck after a point and simulating at xyz nanoseconds/sec, which is obnoxiously slow.

My questions are:
1. Is my approach correct?
2. Is my circuit and script implementation, correct?
3. If the answer to either of the above is no, what should I do/change?
4. How do I speed up the transient response? (if possible)

Attached are relevant images of circuit and its frequency response, and the .asc files used by LTSpice. Any help would be appreciated


 

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Don't see where testpoint is. -164 dB AC gain suggests wrong operation point, check output DC current. Generic "PMOS" is probably not the transistor you want.
 

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I think the components of the snubber circuit are worth rechecking. incorrect values can affect stability.
 

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FvM said:
Don't see where testpoint is. -164 dB AC gain suggests wrong operation point, check output DC current. Generic "PMOS" is probably not the transistor you want.
Click to expand...
hello yes, my bad, i uploaded the wrong screenshot, here's the correct one. The testpoint is the node that connects to R1, R5, and the PMOS
 

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FvM said:
Don't see where testpoint is. -164 dB AC gain suggests wrong operation point, check output DC current. Generic "PMOS" is probably not the transistor you want.
Click to expand...
Selecting an actual PMOS seemed to do the trick for now, along with varying Csnub value accordingly, w.r.t. the gate capacitance of the slected PMOS. Didn't find an exact match, but I think the one in circuit now, is a close substitute. This solves the issue of the weird gain for now, will update on the stability analysis, if it goes well. In the meanwhile, any suggestions for increasing the transient analysis speed?
 

Attachments

  • circuit diagram im.png
    35.2 KB · Views: 67

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Your priotities (bandwidth, phase margin, large signal) aren't clear.

I doubt that "snubber" compensation topology ist best choice.
 

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"Instrument up" the input difference voltage using A=1 vccs to create a ground referred image of the input differential mag / phase.
That is what you need for gain (mag ratio) and phase (phase difference).
 

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crutschow said:
As FvM asked where is "Testpoint"?

Post your LTspice .asc file.
Click to expand...
I have attached an updated reference image in a reply above. PFA the .zip containing the updated circuit, you might observe some changes, namely, using IRF9Z24S as PMOS, and changing Csnub to 36.63nF.
 

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  • current reg ac.zip
    913 bytes · Views: 66

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Feedback wrongly connected in latest circuit.
--- Updated ---

Also current setpoint too high. Either reduce rload or current setting.
 
Last edited:

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