Need help on my two CMFB in the two stage amplifier!

[kongququ]

I design a two stage opamp.
And I probe output of each stage.

When I use the command
Vinp vinp 0 dc=sin(1.5 100u 50k 0 0 0),ac=1,0
Vinn vinn 0 dc=sin(1.5 100u 50k 0 0 180),ac=1,180
.tran 0.2u 2m

the output of each stage of amplifier is good

And when I change the time increase of tran to
Vinp vinp 0 dc=sin(1.5 100u 50k 0 0 0),ac=1,0
Vinn vinn 0 dc=sin(1.5 100u 50k 0 0 180),ac=1,180
.tran 0.1u 2m

The output of each stage is totally wrong.
So how to set the time increase of tran?

thanx

 

[Btrend]

1.I don't think ".tran 0.1u 2m" will less accurate than " tran 0.2u 2m".
maybe what u think it is correct in "tran 0.2u 2m" is wrong.
and what u think is wrong in "tran 0.1u 2m" is correct.
I suggested u should first run AC characteristics of that OP, than u know what ur UGB is, and then u will know ur phase margin.
2. try use .options accurate
to check it again

 

[amraldo]

I agree with Btrend.
BTW the step number differs only as follows:
Accuracy comes from the internal step of the transient analysis. ur simulator acctually calculates at multiples of this internal steps & uses thes values in a linear interpolation to plot the graph at ur step.
.tran[/op] tstep tstop [tsart] [tinternal step] [uic]

 

[kongququ]

Thank you! Btrend&amraldo
I want to know how to choose the suitable time step in Trans and how to find my internal step??

Best regard

 

[Btrend]

Thank you! Btrend&amraldo
I want to know how to choose the suitable time step in Trans and how to find my internal step??

Best regard

it's just like how fast the sampling rate of ur oscilloscope should be in order to measure ur system runing at frequency f Hz. theoretically 2f (nyquist rate) is enough, but u need an ideal LPF to reconstruct (i.e. interpoltaion) ur signal. In real life, there is no ideal LPF, so u should always use much higher sampling rate to record ur signal. usually 10*f is sufficient.
But how much is the value of "f" in ur circuit ?
in digital system, there is always a system clock with f Hz, no doubt , this is ur f,
in analog system, it is always noisy, including feedback path (negative ,positive), sampling noise, clock feedtrhough noise, thermal noise, flicker noise.... some noise are frequency dependent, some are not. but simulator can only calculate some of them. so u should always run AC simulation first to find the UGB (unity gain bandwidth), then choose ur sampling rate as 10*UGB or higher. spice has more elaorate algorithm to improve this setting, but u should provide it with enough information , like step in (.tran step final).
hopes this help u