Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

need help of solving spike Vg induced by Vd on MOSFET.

Status
Not open for further replies.

G35

Newbie level 3
Newbie level 3
Joined
Feb 23, 2006
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,317
fet output spike

Here are my quesoins:
1. will Vd induce spike voltage (noise) at Vg for a MOSFET?
2. If so, how can I eleminate the spike voltage so that Vg is not effected by Vd?
 

formula to find vd in mosfet

G35 said:
Here are my quesoins:
1. will Vd induce spike voltage (noise) at Vg for a MOSFET?
2. If so, how can I eleminate the spike voltage so that Vg is not effected by Vd?

In some high speed comparators, the influence from Vd to Vg is called "kickback noise". There are some techniques to reduce the kickback noise.
1.Neutralization Technique
2.Isolation Techniques, that means place preamplifier beforce the dynamic latch.
Google "kickback noise", you can find some papaers to deal with this problem.

sixth
 

    G35

    Points: 2
    Helpful Answer Positive Rating
how to reduce the voltage spike in mosfet

Thx for your post. However, I am not using it in a comparactor. I just use it in a brushless motor. The drain connects to a coil, which is connected to Vcc. And the source is connected to the ground. and gate voltage comes from an output of a microchip range from 0V to a turnon voltage. However, the gate voltage has some noise when it turns off the MOSFET, which is induced by the drain. is there any other motheds to eleminate the noise? I want the gate voltage goes to the 0V without swinging.
 

voltage spike get rid

Pararell a resistor to g and s
 

spike on low gate mosfet

G35,

yes, voltage spike on the drain can effect the gate voltage. The reason for this is the gate-drain (Miller) capacitance of the FET. Have you tried to limit the spikes on the drain by using a snubber circuit from drain to source? The snubber would either be a RC or a RC+diode circuit. Before putting anything else around the circuit I would try the snubber.

Best regards,
v_c
 

    G35

    Points: 2
    Helpful Answer Positive Rating
mosfet spiking

RC circiut is a good idea. However, it couldn't help at a high frequency because the drain is connected to a coil which connects to a PWM. Actually the spike is fine. What really causes the problem is the fall of the spike. It generates a swing and this swing affects the gate voltage. and I am trying to get rid of the voltage swing at the drain. Anyway, thank you guys for all your inputs.
 

mosfet spike

try to lower mosfet input resistance by resistor connected to gate source . Or better to use low output impedance buffer (current booster) before mosfet .

But what is the spike parameters - rise time, amplitute and others and type of mosfet you use?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top