module ShiftRegister8(input sl, sr, clk,input[7:0] ParIn,input[1:0] m,outputreg[7:0] ParOut);always@(negedge clk)begincase(m)0: ParOut <= ParOut;1: ParOut <={sl, ParOut [7:1]};2: ParOut <={ParOut [6:0], sr};3: ParOut <= ParIn;default: ParOut <=8'bX;endcaseendendmodule// Test bench that i have tried but not working module TB_ShiftRegister8();reg sl, sr, clk;reg[7:0] ParIn;reg[1:0] m;wire[7:0] ParOut;initial$monitor("SL: %b , SR: %b , PARIN: %b , M: %b , PAROUT: %b ", sl, sr, ParIn, m, ParOut);initialbegin#10 sl =1; ParIn =8'b1; m =0;#10 sr =1; ParIn =8'b1; m =1;#10 sl =1; ParIn =8'b1; m =2;#10 sl =1; sr =1; ParIn =8'b1; m =3;#10$stop;end
ShiftRegister8 M0 (sl, sr, clk, ParIn, m, ParOut);endmodule
You didn't originally apply any of the inputs based on a clock so your output is going to match whatever you stimulate the design with.
So your output is correct based on your testbench. If you want it to shift more then you'll have to make sure the signals don't change until you've done all the required shifts.