hello every one, can anyone please tell me what is the value of write_index in the 1st if statement and in the second if statement? and what does the statement STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8)) mean, does it mean we shud consider vectors from 100 upto 8? kindly reply
Code:
signal write_index : std_logic_vector(7 downto 0);
begin
if(start_signal ='1') then
write_index <= std_logic_vector (unsigned(write_index) + 1);
end if;
if(write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8)) then
last_write <= '1';
end if;
it is functioning under axi_m_clk only i didnt mention, kept it simple, is he counting the number of representation of the std_logic_vectors, means making (8 downto 0) then (9 downto 0) ....and so on?? Ok what is the meaning of the second if statement?
Code:
process(M_AXI_ACLK)
begin
if (rising_edge (M_AXI_ACLK)) then
if (M_AXI_ARESETN = '0' or init_txn_pulse = '1') then
-- reset condition
last_write <= '0';
else
--The last write should be associated with a write address ready response
if (write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8)) and M_AXI_AWREADY = '1') then
last_write <= '1';
end if;
end if;
end if;
end process;
in case of complete process info, what is he doing here [write_index = STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8))]? i dint understand this one?
It is setting write_index to 100.
The second part:
STD_LOGIC_VECTOR(TO_UNSIGNED(100, 8))
Is all just a type conversion to get 100 into a std_logic_vector. This shows some poor type choices in the code. write_index should be an unsigned or an integer to avoid so many conversions.
What your code describes is a positive edge triggered DFF an enable and synchronous reset.
I rewrote ( It's function remains absolutely equivalent ) - perhaps it'll be easier to understand this way:
Code:
-- Combinatorial Logic
reset_condition <= ( not M_AXI_ARESETN ) or init_txn_pulse ;
last_write_condition <= '1' when write_index = "01100100" and M_AXI_AWREADY = '1' else '0' ;
-- Synchronous logic
process ( M_AXI_ACLK )
begin
if rising_edge ( M_AXI_ACLK ) then -- M_AXI_ACLK is the DFF clock
if reset_condition = '1' then -- DFF synchronous reset
last_write <= '0' ;
elsif last_write_condition = '1' then -- DFF enable
last_write <= '1' ;
end if;
end if;
end process ;
@op, this is code that has formed due to a few issues. The main issues are two conflicting design philosophies.
1.) Numeric operations can only be used on numeric types. (std_logic_vector has a defined ">", but it should never be used.)
2.) std_logic_vector is required for all ports. (existing code did this, and this remained a prevalent style for a long time.)
There are two solutions to the problem.
1.) std_logic_unsigned/numeric_std_unsigned -- allow std_logic_vector to have numeric operations and be treated as unsigned. (std_logic_unsigned will cause you to not be taken seriously as a developer. numeric_std_unsigned is vhdl2008.)
2.) use numeric types for any ports treated as numbers. (existing code used only std_logic_vector. RAMs are almost always std_logic_vector -- some conversions will still be required.)
Given these options, many developers choose to do neither. Instead they start with a mix of std_logic_vector and unsigned. Eventually they realize that it is annoying to micro-manage types when few mathematical operations are used. This leads to the double-conversion style, where math operators are done by converting std_logic_vector to unsigned, then converting the result back to std_logic_vector. The double conversion style places the micro-management on very few lines of code where math is actually used. This isn't intended as a defense of this style, just an explanation of where it comes from.
Correct.
The "to_unsigned" is necessary because "100" is an integer and because VHDL is a strongly typed language a comparison between an integer and an Unsigned is illegal.
Correct.
The "to_unsigned" is necessary because "100" is an integer and because VHDL is a strongly typed language a comparison between an integer and an Unsigned is illegal.
Comparison between unsigned and integer is legal as "=" is defined in numeric_std. But comparison between std_logic_vector and integer is not defined in standard VHDL