Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Need help in regards to low jitter PFD topologies

Status
Not open for further replies.

Lightening

Newbie level 1
Newbie level 1
Joined
Nov 22, 2005
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
Hi All

Anybody have experience with Low jitter PFD topologies. Not at the gate but basic building block level.

So, I am confussed over various text that desscribe Alexander, Hogge and the the basic PFD using two D flip flops and a nand gate with feeding back to the reset via delay circuit.

Which circuit has best phase noise performance, no dead zone and most importantly why.

My application is at quiet low frequency < 100MHz. Of course in general the faster the circuit the less jitter.

All help very much appreciated.

Thanks Lightening
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top