ok.
I now post the schematic in the attachment.
M1~M6 is core circuit. M7 and M9 is for further current mirrori. MS0~MS3 is a start up circuit.
I read some papers. According to these papers, if M1 and M2 are in weak inversion, the current of the circuit is reasonable to show PTAT property. I have
find it in my simulation result.
And according to other papers , if M1 and M2 are in saturation , the current should
be independent of temperature. I just can not implement it. In the simulation, when the output current is less insensitive to temperature, some transistors(M3 and M6) are in linear region and the current varies in wide ranges between different design corner( tech corner & supply voltage). It is clear to be not acceptable.
Thanks for ur help.
Here is my netlist and my simulation output in HSPICE. The figure is also in the attachment. There are 15 curves of different design corners.
NETLIST:
M1 2 1 3 VSS Nch3 L=4U W=10U M=4
M2 1 1 VSS VSS Nch3 L=4U W=10U M=1
M3 5 4 2 VSS Nch3 L=4U W=2U
M4 4 4 1 VSS Nch3 L=4U W=2U
M5 5 5 VDD VDD Pch3 L=4U W=10U M=2
M6 4 5 VDD VDD Pch3 L=4U W=10U M=2
M7 OC 5 VDD VDD Pch3 L=4U W=10U M=20
M9 OC OC VSS VSS Nch3 L=4U W=10U M=2
MS0 S0 VSS VDD VDD Pch3 L=10U W=0.4U
MS1 S1 VSS S0 VDD Pch3 L=10U W=0.4U
MS2 5 S1 VSS VSS Nch3 L=0.5U W=15U
MS3 S1 1 VSS VSS Nch3 L=0.5U W=15U
xRS1 3 VSS rnpo1rpo l=50u w=4u $Rsquare=180