[SOLVED] Need HELP in Cadence Layout LVS using GF 22nm FDSOI! Error: Different numbers of ports

[cookies1427]

Can anybody help out a beginner here? I keep having this discrepancy error in my lvs report talking about these missing ports. Upon looking at different forums, it always says that I have to use a specific type of metal layer. So, I made sure that the nets have M1 pin layer similar with its label. Since it is also said that it is case sensitive, I made sure to name them properly.

After all these, these errors keep showing. I have attached the necessary screenshot in my layout.

Any answer is highly appreciated. Thanks boss!

 

[sidun.av]

Hi @cookies1427 ,

Different manufacturers have different rules for pin/label layer definitions. The easiest way to figure that out is to take any standard cell (for example, from the digital library, let's say, an inverter), place it into the layout and check which layer is used for the pin/label. You can do so by filtering "only used" layers and turning on/off the corresponding metal.
Hopefully, that helps.

 

[sidun.av]

Hi @cookies1427 ,
If you solved your issue, please share the solution for the benefit of others. Thank you.

 

[cookies1427]

Hi @sidun.av thank you very much for your help and sorry I didn't get back sooner. I did as you instruct and analyzed the cell and found out the solution. I was so excited that I finally cleared my LVS report that I forgot to get back to this post. Hahahaha

So the solution was as simple as keeping the purpose of the metal layer as strictly as possible. So, I used M1 pin for my "in" net but problem arises when I also choose M1 pin for the label. So I put changed the label in M1 with its purpose as "label" or in some cases "lbl". In that way, the lvs have finally recognized the nets as ports!!!