need help from vhdl developer?

[senthilkumar]

vhdl std_logic to boolean

Hai.

i write the code like this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity vga is
Port ( clk_raw : in std_logic;
vsync : out std_logic;
hsync : out std_logic;
r : out std_logic_vector(1 downto 0);
g : out std_logic_vector(1 downto 0);
b : out std_logic_vector(1 downto 0));
end vga;

architecture Behavioral of vga is
constant CounterXMax: INTEGER := 767;
--constant CounterYMax: INTEGER := 31;
signal clk_div:std_logic_vector(1 downto 0);
signal clk:std_logic;
signal CounterX:std_logic_vector(9 downto 0);
signal CounterY:std_logic_vector(9 downto 0);
signal vga_HS:std_logic;
signal vga_VS:std_logic;

begin

process(clk_raw)
begin
if(clk_raw 'event and clk_raw='1')then
clk_div<=clk_div+1;
clk<=clk_div(1);
end if;
end process;

process(clk)
begin
if(clk 'event and clk='1')then
if(CounterXMax=767)then
CounterX<="0000000000";
else
CounterX<=CounterX+1;
end if;
end if;
end process;

process(clk)
begin
if(counterXMax=511)then
if(CounterY=511)then
CounterY<="0000000000";
else
CounterY<=CounterY+1;
end if;
end if;
end process;







--process(clk)
--begin
-- if(clk 'event and clk='1')then
-- vga_hs<=count
-- end if;
--end process;

PROCESS
BEGIN
WAIT UNTIL (clk'EVENT AND clk = '1');
vga_HS <= to_bit(CounterX(9 DOWNTO 4) = "101101");
vga_VS <= to_bit (CounterY = "111110100");
END PROCESS;



end Behavioral;


after i synthesis ,i i got tthe error like this



Started process "Synthesize".


=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file D:/work/XessBoard/vga_vhdl_test/vga.vhdl in Library work.
ERROR:HDLParsers:808 - D:/work/XessBoard/vga_vhdl_test/vga.vhdl Line 78. to_bit can not have such operands in this context.
ERROR:HDLParsers:808 - D:/work/XessBoard/vga_vhdl_test/vga.vhdl Line 79. to_bit can not have such operands in this context.
-->

Total memory usage is 45400 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.



How can i solve that one.

any alternatice code ???
:roll: :roll: :roll:

 

[moira]

or can not have such operands in this context

u want to generate the timing of VGA,right?
i've written one that is similar to urs,according to ITU- RBT 601,and i use quartusii .
i couldn't understand ur code.
u could write me ,and we can discuss it

 

[zhuoyue]

to integer cannot have such operands vhdl

some funcation isn't avaliable ,you can ref the ieee library

 

[jelydonut]

hdlparsers:808

which lines are 78 and 79? Remember people are lazy and don't wanna hafta search..

jelydonut

 

[Husoo]

vhdl std_logic-to-boolean

try to use if-clause instead to_bit()

e.g.: if cond the vga <='1'; else vga <= '0'; end if;

 

[leonyang]

error:hdlparsers:808 read file

The conversion function to_bit() in the std_logic_1164 package can not apply to the boolean type operand. You can overload it to implement what you want.

 

[vomit]

requirements of vhdl developer

Hai.

signal vga_HS:std_logic;
signal vga_VS:std_logic;
vga_HS <= to_bit(CounterX(9 DOWNTO 4) = "101101");
vga_VS <= to_bit (CounterY = "111110100");
ERROR:HDLParsers:808 - D:/work/XessBoard/vga_vhdl_test/vga.vhdl Line 78. to_bit can not have such operands in this context.
ERROR:HDLParsers:808 - D:/work/XessBoard/vga_vhdl_test/vga.vhdl Line 79. to_bit can not have such operands in this context.

Have a look at http://www.eda.org/rassp/vhdl/guidelines/1164qrc.pdf section 1.4

You'll see that the to_bit() function converts FROM std_logic TO boolean, and you want the other way round.

Use to_stdulogic() instead.

 

[vvsvv]

vhdl to_bit function

I am doing video acquicision too,
you may copy one of your source code to my email.
then Let's discuss it then!

s20020423@eyou.com